Non AMP

Multidriven Signals due to for loop in verilog

Thread starter hassanzia
Start date Jan 27, 2013

Status: Not open for further replies.

Jan 27, 2013

#1

H

hassanzia

Junior Member level 3

Hi all,

if A,B and C are 8 bit deep RAMS then why does this code produces a multidriven signal error

Code:

for (i=0;i<16;i=i+1)
begin
  for (j=0;j<8;j=j+1)
    begin
      A[i][j] = B[i][j] ^ C[i][j];
    end
end

whereas this one produces no error

Code:

for (i=0; i<16; i=i+1)
begin
  A[i] = B[i] ^ C[i];
end

Status: Not open for further replies.

Similar threads

E
Which simulator should I use for verilog?
- Started by electronicslab
- Oct 26, 2024
- Replies: 9
PLD, SPLD, GAL, CPLD, FPGA Design
T
Comparing differential signals without comparator
- Started by Tajira
- Jul 24, 2024
- Replies: 10
PLD, SPLD, GAL, CPLD, FPGA Design
E
Is there anything that converts verilog to resistor, capacitor level design?
- Started by electronicslab
- Oct 27, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
B
[SOLVED] Writing a verilog code to generate a single pulse?
- Started by BALU@FPGA
- Jul 23, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
E
Which one should I learn today? Verilog or Systemverilog?
- Started by electronicslab
- Oct 27, 2024
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design