multibit delta sigma DAC using FPGA

[cdcll]

delta sigma dac on fpga

any one can give me information about multibit delta sigma DAC implementation using FPGA?

Thanks!

 

[Big Boy]

design a delta sigma dac example low pass filter

Look for Xilinx app. notes XAPP154

 

[cdcll]

which dac output is suited for fpgas

Big Boy,thank you! I downloaded the Xilinx app. notes XAPP154, the ref. design looks like a single-bit delta sigma DAC implementation, could you recommend a ref. design for multi-bit delta sigma DAC?

 

[Big Boy]

delta-sigma dac in fpga

Depend on what you meen by multi-bit.

By design, a Delta-Sigma DAC is a 1-bit output device. You can have multiple bits precision. For example, you could have a 16-bit input Delta-Sigma DAC.

How it work is that it modulate the output bit so that over repetitive periods of time, which period can be very small (high frequency), the average level represent the input value.

So, for example, in an 8-bit unsigned Delta-Sigma DAC, if you would input a value of 128, you would get an output which is in average 50% of the total output range (50% between 0V and 3.3V for example). In other words, 50% of the time, the DAC output 0V, and 50% of the time, it output logic 1 (3.3V for example).

By placing a resistor/capacitor at output, this will filter the high frequency output of the DAC, and only give you the average.

The important factor is to choose the correct R and C values. R*C too low will not filter high frequency output of the DAC enough. Too low, it will act as a low-pass filter, actually cutting too much.

Those DAC are best suited for audio, and are in fact one of the highest quality DAC for audio.

So, I don't know if this answer your question, or if you meen something else by 'multibit'.