[SOLVED] Multi source error in VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity DeModulator is
    Generic
	      (
	       symbolLength : integer := 8
	       );
    Port (
           clk_demod              : in  STD_LOGIC;
	  reset_async             : in  STD_LOGIC := '0';
	  reset_sync              : in  std_logic := '0';
	  data_valid_noise_out : in  STD_LOGIC := '1';
          data_mod                : in  STD_LOGIC_VECTOR((2*symbolLength -1) DOWNTO 0) := "1001010111101011";
	  data_valid_demod     : out STD_LOGIC;
          data_demod             : out STD_LOGIC_VECTOR((symbolLength -1) DOWNTO 0)
            );
end DeModulator;

architecture RTL of DeModulator is
   signal data_demodulated     : STD_LOGIC_VECTOR((symbolLength -1) DOWNTO 0) := (others =>'0');
begin
---------------------------- Reverse of mod is performed ----------------------------------
Generate_demod : for i in 0 to symbolLength - 1 Generate
process (clk_demod, reset_async)
begin 
   if reset_async = '1' then 
      data_valid_demod <= '0';
   elsif rising_edge(clk_demod) then 
      if reset_sync = '1' then 
         data_valid_demod <= '0';
      elsif data_valid_noise_out = '1' and data_mod(2*i+1) = '0' then 
         data_demodulated(i)   <= '1';
        -- data_valid_demod  <= '1';
      elsif data_valid_noise_out = '1' and data_mod(2*i+1) = '1' then
         data_demodulated(i)   <= '0';
      	--data_valid_demod  <= '1';
      else
      	data_valid_demod   <= '0';  
         data_demodulated(i)    <= data_demodulated(i);     
      end if;
   end if;
end process; 
end Generate;