Multi-fingers in MOSFET in Series configuration in Cadence Virtuoso Schematic

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aguntukbd

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I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both p-mos & n-mos). I know I can increase the length directly. As connecting MOSFET in series increases length, can I somehow configure the finger properties (nf > 1) of MOSFET in such a way that S/D of each finger connects as series? I am asking to do it in schematic, not in layout yet.
I am using Cadence Virtuoso and 22nm technology.
 

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The term "multi-finger device" usually implies a parallel - not series connection of multiple devices (instances).
nf parameter means - how many fingers are there, in parallel.

For series connections, people usually call them "stacked devices".
 
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Thanks timof. I realized the thing that I wanted is not possible in schematic level for transistors. Thoguh I have no idea about the term of "stacked devices". Can transistor be stacked device in the model so that it can be used in schematic?
 

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Stacked device will not come in the technology library, neither can you configure it by changing any settings. You will have to manually stack the devices, which is like a cascode device with gate tied to the main device. This will almost behave like 2x length device for output impedance, but not exactly the same as doubling the length of the device.
 
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aguntukbd said:
Thanks timof. I realized the thing that I wanted is not possible in schematic level for transistors. Thoguh I have no idea about the term of "stacked devices". Can transistor be stacked device in the model so that it can be used in schematic?
Click to expand...

Normally, each "finger" (for either parallel or series connections) will have its own instance (in LVS and in extracted netlist), described by a SPICE model with a unique set of instance parameters.

For some popular and important type of devices - for example, where a high accuracy of SPICE model is required, such as RF MOSFET - foundries would create P-CELLs, that have their own SPICE models, for fixed geometry/topology. These models are very accurate, but not scalable (you can't define your own device width, for example). Also, they may require some additional structures, like guard rings, to shield the device form the outside world (from the interconnects and other devices), that take a lot of space, and that's why people may not like them.
 
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Thanks timof and AMS012 for your knowledge sharing. I will try in layout to do that. I may ask more questions when needed in layout phase
 

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If you are stacking devces for voltage standoff then you need
independent bodies, else G-B breakdown will be the failure.
Done this a lot on SOI, impractical for mainstream LV CMOS
without a triple well process.

In schematics you can draw (3) nf=1 FETs and lay them out in
a "stack" and get LVS to pass. But the common body is still an
issue (first order, for breakdown / impact ionization voltage;
second order, for body effect on circuit behavior).
 

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