digitalo
Junior Member level 1
Hi all!
I have a situation where two clocks that are in phase reach my digital block. The only difference between the signals is that different clock gating has been applied.
Now I need to define a multi-cycle path between these two clocks. When I just define the multi-cycle path, it is applied correctly, but does not lead to the desired result. The worst hold path is calculated for early and late clock starting at the same time.
So I end up with a hold violation. But actually, there are several 10 ns slack, when the multi-cycle path is considered correctly.
Apparently I need to be more specific about the phase relationship between the clocks. I tried adding waveform information to the create_clock calls, but [0 15] is anyway the default.
My first idea was to define a virtual clock and then both actual input clocks as derived clocks. But since I cannot derive a clock from a virtual clock, this led nowhere.
Is there a good way to say that two input clocks are essentially identical?
Or to describe the multi-cycle path in another way?
I'm close to just disabling hold timing checks between the clocks. A hold violation starting with clocks 60 ns apart is not so likely, after all...
Thanks, digitalo
I have a situation where two clocks that are in phase reach my digital block. The only difference between the signals is that different clock gating has been applied.
Code:
create_clock -name "clk_dr" -period 30.0 [get_ports {CLK_DR}]
create_clock -name "clk_update_dr" -period 30.0 [get_ports {CLK_UPDATE_DR}]Now I need to define a multi-cycle path between these two clocks. When I just define the multi-cycle path, it is applied correctly, but does not lead to the desired result. The worst hold path is calculated for early and late clock starting at the same time.
Code:
Capture Launch
Clock Edge:+ 30.000 30.000
Code:
Applied exceptions:
----------------------------------------------------------------------------------------------------
From To Early Late View
Name
----------------------------------------------------------------------------------------------------
"clk_dr" "clk_update_dr" cycles 1 - jtag_ss_60_cworst
"clk_dr" "clk_update_dr" - cycles 2 jtag_ss_60_cworst
-----------------------------------------------------------------------------------------------So I end up with a hold violation. But actually, there are several 10 ns slack, when the multi-cycle path is considered correctly.
Apparently I need to be more specific about the phase relationship between the clocks. I tried adding waveform information to the create_clock calls, but [0 15] is anyway the default.
My first idea was to define a virtual clock and then both actual input clocks as derived clocks. But since I cannot derive a clock from a virtual clock, this led nowhere.
Is there a good way to say that two input clocks are essentially identical?
Or to describe the multi-cycle path in another way?
I'm close to just disabling hold timing checks between the clocks. A hold violation starting with clocks 60 ns apart is not so likely, after all...
Thanks, digitalo