multi-bit sigma-delta modulator

[qslazio]

i'd like to design a SC sigma-delta modulator with multibit (4bit) quantizer (using flash ADC) in the forward path.
I'm wondering how large the power of the 4-bit quantizer will consume.
And will it dominate in the total power consumption of modulator?

Thanks
qs

 

[radigital]

Yes it may dominate the total power consumption, because a 4-bit flash ADC has
around 15 comparators. Furthermore the comparators may need precise design
and matching requirements, because mismatch in them can distort the linearity
of the overall implementation. Or you need to use dithering, to compensate the
non-linearity.

 

[qslazio]

thanks to radigital!
i'd like to know whether there is some approach to achieve 4-bit quantization with relative low power consumption.

 

[mr_chip]

It depends on the spec of the SD ADC as well as it's architecture - there's no general answer if internal ADC will dominate power consumption.

But in my experience, the internal quantizer is not the major contributor to overall power consumption. Usually OTAs in the loop filter (especially in the first integrator) consume more current.

Usually the requirements to the linearity of the internal ADC in the quantizer are not very strict, because it is in the loop, so it's error is noise-shaped. Low hysteresis is a more important then offset.

However the linearity of the feedback is VERY important, so usually special techniques are used to improve it.