mohammadmother
Junior Member level 3
- Joined
- Oct 2, 2012
- Messages
- 26
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,471
Hi
my working is to implement a circuit in FPGA ,i get the admittance
matric of circuit that be multiply it into current vector(value of
current vector changing with control signal state)
when the clock rise(posedge), elements of inverse admittance matric
(G11,G12,G21,G22) multiply into vector of current and when the clock
down(negedge), the vector of current be updated.
the code has been written in verilog.
what is the problem of these code?
thanks a lot
my working is to implement a circuit in FPGA ,i get the admittance
matric of circuit that be multiply it into current vector(value of
current vector changing with control signal state)
when the clock rise(posedge), elements of inverse admittance matric
(G11,G12,G21,G22) multiply into vector of current and when the clock
down(negedge), the vector of current be updated.
the code has been written in verilog.
what is the problem of these code?
thanks a lot
PHP:
[syntax=vhdl]
[VHDL]
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:30 10/24/2014
// Design Name:
// Module Name: scircuit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scircuit(
input control,
input clk,
input reset,
inout reg [15:0] v1,v2
);
parameter r1=1, G1=1 , R=1010, vdc=1100100;
parameter y11=(1/r1)+G1 ,y12=-G1 ,y21=-G1 ,y22=R+G1;
parameter yy=1/((y11*y22)-(y12*y21));
parameter G11=y22/yy ,G12=-y12/yy ,G21=-y21/yy ,G22=y11/yy;
reg signed [15:0] j1,j2;
always @(posedge clk)
if (reset == 1)
begin
v1 <= 16'b0000000000000000;
v2 <= 16'b0000000000000000;
end //end if(reset ==1)
else
begin
i1 <=(vdc/r1)+j1;
i2 <= -j1;
v1 <= (G11*i1) + (G12*i2) ;
v2 <= (G21*i2) + (G22*i2) ;
end
always @(negedge clk)
case(control)
1'b1:
begin
j1 <=-G1*(v1-v2);
end
1'b0:
begin
j1 <= G1*(v1-v2);
end
end case
endmodule
[/VHDL][/syntax]
Last edited by a moderator: