MPQ4470-AEC1 Layout guideline clarification

Status
Not open for further replies.
N

newbie_hs

Full Member level 2
Joined
Mar 4, 2023
Messages
129
Helped
1
Reputation
2
Reaction score
1
Trophy points
18
Activity points
1,025
Dear Team,

I am using MPQ4470-AEC1 in my design. In the datasheet page no 18 contains the layout guidelines.

I have some questions about guideline no:2 and no:3 .Those guidelines are given below.

  1. Place input capacitors on both VIN sides (PIN8 and PIN19) and as close to the IN and GND pins as possible.
  2. Place the decoupling capacitor as close to the VCC and GND pins as possible


Regarding placement ,they said only 'close' .
My question is how to calculate the maximum and minimum distance away from the IC so that I can place the parts(Capacitor).

Regards
 

Sort by date Sort by votes
The layout picture clarifies what "close" means. I'd translated it as minimal distance achievable with reasonable component spacing according to design rules.

 

Upvote 0 Downvote
I completely agree with you.
But May I know how to calculate the distance theoretically
 

Upvote 0 Downvote
Minimal distance is monitored by your layout tool according to design rules in effect. Refer to assembly house requirements and IPC.

Maximal distance can't be simply calculated. You can estimate trace inductance by rules of thumb or determine it exactly in a FEM simulation. Know capacitor parasitic impedance and put all parameters in a SPICE simulation. Or just place capacitors "as close as possible" and verify switcher performance in real hardware.
 

    N

    newbie_hs

    Points: 2
    Helpful Answer Positive Rating
Upvote 1 Downvote
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…