[Moved]: XOR output problem in hspice

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discover93

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Hello guys.
I am using Hspice to simulate 2-input xor gate., but for some reasons the output is not as neat as I expected. I will be very thankful if someone explain me the reason.
Here is the code:

Code: 
#xor 

.option nomod
.include ./22nm_lp.pm.txt
.include ./inverter.sp

X_invertera 1 a ab inverter
X_inverterb 1 b bb inverter

M1 2 a  1 1 pmos l=22n w=33n 
M2 c bb 2 2 pmos l=22n w=33n  
M3 3 ab 1 1 pmos l=22n w=33n 
M4 c b  3 3 pmos l=22n w=33n  


M5 c a  4 4 nmos l=22n w=33n 
M6 4 b  0 0 nmos l=22n w=33n 
M7 c ab 5 5 nmos l=22n w=33n 
M8 5 bb 0 0 nmos l=22n w=33n 

vdd 1 0 dc 0.95V
vinb b 0 pulse(0.95 0 0 10p 10p 95p 200p)
vina a 0 pulse(0.95 0 50p 10p 10p 95p 200p)
.tran 200p 600p

.end



.subckt inverter 1 a b

.option post accurate nomod
.include ./22nm_lp.pm.txt

M1 b a 1 1 pmos l=22n w=33n *Ap

M2 b a 0 0 nmos l=22n w=33n *An

.ends
 

Re: XOR output problem in hspice

Hi,

It seems the output is not like expected.
But what did you expect?
Delays?
Rise/fall times?

Klaus
 

Re: XOR output problem in hspice

The XOR logic function seems correct.

Apparently you have unrealistic expectations regarding circuit speed or signal levels. How do you know that the circuit can work at GHz speed?
 
Re: XOR output problem in hspice

Your netlist appears to contain mosfets. If you were to use transistors then they may give you better 'snap action'.

The webpage below has several logic schematics made from discrete devices, including Exclusive-Or gates.

https://www.4qdtec.com/dlc.html
 

Re: XOR output problem in hspice

The webpage below has several logic schematics made from discrete devices
Click to expand...

I doubt that the simple diode transistor logic is going to work above e.g. 10 MHz switching frequency. Using CMOS at multiple GHz should be possible, but there are some requirements for transistor technology.
 
Re: XOR output problem in hspice

I'm so new to the topic but thanks to your replies, I now understand that frequency I set was not a good idea.
One main problem I have with this and many other gates as well, is the spikes of voltage before rise and fall. I want to know why there are spikes and how can I decrease them.

- - - Updated - - -

Thanks for your reply. You are right. I don't have good knowledge on topic.
Can you explain signal levels a little more.
 
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