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Digital Design and Embedded Programming
PLD, SPLD, GAL, CPLD, FPGA Design
[Moved]Verilog issue with output even though condition is met(dice game)

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[QUOTE="dpaul, post: 1782592, member: 151192"] [HEADING=3]@[USER=690860]ralph_verilog[/USER][/HEADING] If you want need help please formulate a question and post at the ASIC or FPGA sub-forum! [/QUOTE]

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Digital Design and Embedded Programming
PLD, SPLD, GAL, CPLD, FPGA Design
[Moved]Verilog issue with output even though condition is met(dice game)

Welcome to EDAboard.com

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@[USER=690860]ralph_verilog[/USER]

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