[Moved]Verilog issue with output even though condition is met(dice game)

[ralph_verilog]

Design:

module dice_game(
    input wire clk,        
    input wire roll,       
    output reg [2:0] die1, 
    output reg [2:0] die2,  
    output reg win          
);

    always @(posedge clk) begin
        if (roll) begin
            die1 <= $urandom_range(1, 6);
            die2 <= $urandom_range(1, 6);
          if ((die1 + die2 == 7) || (die1 + die2 == 11))
                win <= 1;
            else
                win <= 0;
        end
      else
        begin
            win <= 0;
        end
    end
endmodule



Testbench:
module tb_dice_game;

    reg clk;
    reg roll;
    wire [2:0] die1;
    wire [2:0] die2;
    wire win;

    dice_game uut (
        .clk(clk),
        .roll(roll),
        .die1(die1),
        .die2(die2),
        .win(win)
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        roll = 0;
        #10;

        repeat (10) begin
            roll = 1;
            #10;
            roll = 0;
            #10;
        end

        #50;
        $finish;
    end

    initial begin
      $monitor("At time %t, roll = %b, die1 = %d, die2 = %d, win = %b", $time, roll, die1, die2, win);
    end

endmodule



Output:
At time                    0, roll = 0, die1 = x, die2 = x, win = x
At time                    5, roll = 0, die1 = x, die2 = x, win = 0
At time                   10, roll = 1, die1 = x, die2 = x, win = 0
At time                   15, roll = 1, die1 = 4, die2 = 2, win = 0
At time                   20, roll = 0, die1 = 4, die2 = 2, win = 0
At time                   30, roll = 1, die1 = 4, die2 = 2, win = 0
At time                   35, roll = 1, die1 = 1, die2 = 2, win = 0
At time                   40, roll = 0, die1 = 1, die2 = 2, win = 0
At time                   50, roll = 1, die1 = 1, die2 = 2, win = 0
At time                   55, roll = 1, die1 = 4, die2 = 5, win = 0
At time                   60, roll = 0, die1 = 4, die2 = 5, win = 0
At time                   70, roll = 1, die1 = 4, die2 = 5, win = 0
At time                   75, roll = 1, die1 = 2, die2 = 1, win = 0
At time                   80, roll = 0, die1 = 2, die2 = 1, win = 0
At time                   90, roll = 1, die1 = 2, die2 = 1, win = 0
At time                   95, roll = 1, die1 = 4, die2 = 4, win = 0
At time                  100, roll = 0, die1 = 4, die2 = 4, win = 0
At time                  110, roll = 1, die1 = 4, die2 = 4, win = 0
At time                  115, roll = 1, die1 = 5, die2 = 4, win = 0
At time                  120, roll = 0, die1 = 5, die2 = 4, win = 0
At time                  130, roll = 1, die1 = 5, die2 = 4, win = 0
At time                  135, roll = 1, die1 = 6, die2 = 5, win = 0
At time                  140, roll = 0, die1 = 6, die2 = 5, win = 0
At time                  150, roll = 1, die1 = 6, die2 = 5, win = 0
At time                  155, roll = 1, die1 = 6, die2 = 3, win = 1
At time                  160, roll = 0, die1 = 6, die2 = 3, win = 1
At time                  165, roll = 0, die1 = 6, die2 = 3, win = 0
At time                  170, roll = 1, die1 = 6, die2 = 3, win = 0
At time                  175, roll = 1, die1 = 3, die2 = 2, win = 0
At time                  180, roll = 0, die1 = 3, die2 = 2, win = 0
At time                  190, roll = 1, die1 = 3, die2 = 2, win = 0
At time                  195, roll = 1, die1 = 6, die2 = 2, win = 0
At time                  200, roll = 0, die1 = 6, die2 = 2, win = 0
testbench.sv:34: $finish called at 260 (1s)

 

[dpaul]

@ralph_verilog​

If you want need help please formulate a question and post at the ASIC or FPGA sub-forum!

 

[FvM]

Moved to FPGA section. As stated by dpaul, please describe the problem you are seeing and ask clear questions, not just drop a question in the title.

Your Verilog code is working as expectable due to Verilog syntax rules.

I guess your problem is that win = 1 appears one roll after the condition is met. But that's exactly what you have coded

---

Code Verilog - [expand]
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if (roll) begin
            die1 <= $urandom_range(1, 6);
            die2 <= $urandom_range(1, 6);
          if ((die1 + die2 == 7) || (die1 + die2 == 11))
                win <= 1;
            else
                win <= 0;
        end

---

Due to non-blocking assignments to die1 and die2, condition is checked one clock cycle later.

=> Learn about behaviour of non-blocking assignments and modify your code respectively.