abdoabd
Newbie level 2
Hi
Info: I am using cadence IC6.1.6 and I have access to Process Design Kits from a commercial foundry (PDKs)
My aim is to have the ability to manipulate the model equations and parameters for the bipolar vbic model (or other models if possible) but for the specific process that I use from the fabrication foundry (the foundry supplies vbic1.1.5 version for simulation). To do that I had to download a veriloga version of the vbic1.1.5 model from www.designers-guide.org/VBIC/ and I added that as a cellview which has all the vbic model parameters in there. My naive thinking was to go to the model library files that we get in the PDKs (same files that I give to spectre to simulate any circuit) and get its entries as the input parameters to my new veriloga transistor and I expected that it will be scaled with the size of the BJT (Emitter Area). The original foundry transistor simulation didn't match with the new veriloga one because that method didn't provide me with the right scaled parameters vs size. This is the only file from the PDKs that I know to have parameter information. So, as a simple question, does the spectre simulator take the model library files' parameters as we see them in the PDK file and then implement the scaling internally in a way that no one can see how this scaling is done?
What exactly is the model library file that is supplied by the foundry in the PDK? Is it the model parameters fixed for a certain size?
Any Suggestion of how to manipulate the model files and parameters in a way to have a veriloga model that matches the foundry transistor in simulation?
Sorry if my question looks ambiguous.
Thanks Everyone.
Info: I am using cadence IC6.1.6 and I have access to Process Design Kits from a commercial foundry (PDKs)
My aim is to have the ability to manipulate the model equations and parameters for the bipolar vbic model (or other models if possible) but for the specific process that I use from the fabrication foundry (the foundry supplies vbic1.1.5 version for simulation). To do that I had to download a veriloga version of the vbic1.1.5 model from www.designers-guide.org/VBIC/ and I added that as a cellview which has all the vbic model parameters in there. My naive thinking was to go to the model library files that we get in the PDKs (same files that I give to spectre to simulate any circuit) and get its entries as the input parameters to my new veriloga transistor and I expected that it will be scaled with the size of the BJT (Emitter Area). The original foundry transistor simulation didn't match with the new veriloga one because that method didn't provide me with the right scaled parameters vs size. This is the only file from the PDKs that I know to have parameter information. So, as a simple question, does the spectre simulator take the model library files' parameters as we see them in the PDK file and then implement the scaling internally in a way that no one can see how this scaling is done?
What exactly is the model library file that is supplied by the foundry in the PDK? Is it the model parameters fixed for a certain size?
Any Suggestion of how to manipulate the model files and parameters in a way to have a veriloga model that matches the foundry transistor in simulation?
Sorry if my question looks ambiguous.
Thanks Everyone.
