[Moved] transistor level code

Similar threads

• E

  Is there anything that converts verilog to resistor, capacitor level design?

  • Started by electronicslab
  • Oct 27, 2024
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• R

  [Moved]Verilog issue with output even though condition is met(dice game)

  • Started by ralph_verilog
  • Oct 21, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  VHDL code to that make text on lcd

  • Started by aiman89
  • Nov 15, 2024
  • Replies: 9

  PLD, SPLD, GAL, CPLD, FPGA Design
• B

  [SOLVED] Writing a verilog code to generate a single pulse?

  • Started by BALU@FPGA
  • Jul 23, 2024
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• S

  Cannot identify inferring latches in code

  • Started by sims0702
  • Apr 12, 2024
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design