[SOLVED] [moved] problem in simulation OTFT verilogA model in cadence

[electronicman26]

hi
I want to simulate the verilogA model of OTFT transistor but see this error:

 

[mosdarsh]

show us the verilog-a file, and how you put it in cadence?

 

[pancho_hideboo]

I want to simulate the verilogA model of OTFT transistor but see this error:

What view do you set in "Switch View List" and "Stop View List" ?

Or use "config view" of Hierarchy Editor to choose veriloga or verilogams view.

 

[electronicman26]

Hi
I want to model a simple resistor with this verilogA code:
module simpleres(a, b);
inout a, b;
electrical a, b;
analog I(a,b) <+ V(a,b) / 1000;
endmodule
I try to do this modeling according to this: http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ICDesignVerilogA
I do steps 1 and 2 but I have problem in step 3, after click a blank veriloga template popup but how I can transfer my code and how I can save it?? what should I do for save the code after type?

 

[mosdarsh]

in cds.log type:
editor="gedit" and press enter