Unfortunate the floating point vendor libraries aren't provided as VHDL sources, most likely they even haven't been written in VHDL or Verilog. They are designed to use the DSP hardware of different FPGA families in an optimal way, using respective low-level primitives. Altera e.g. is typically writing this stuff in AHDL.
For the same reason, writing your own float libraries will probably not cope with the performance of the vendor libraries.
I'm not sure what's the focus of your project. If you're mainly interested in functional floating point code and don't care for performance, you can refer to the IEEE float package. It's completely missing pipelining and thus won't be used for hardware synthesis as is, but it's pure VHDL code. You can add pipelining on your own.
There are surely other projects of floating point code dedicated for hardware design. To locate it, you should start your own web search.
Another reasonable approach would be writing a floating point multiplier from the scratch.