[SOLVED] [Moved.]Maximum Vdd in BiCMOS Processes

Hi, I am unclear on what the meaning of "Maximum Vdd" and "Vdd" in mixed signal design with BiCMOS processes. I am designing a DAC that has both digital and analog sections. My question may be split into the the digital and analog sections.

1. What does Vdd mean for digital sections? The digital sections are typically deigned with nMOS transistors.
2. What does Vdd mean for analog sections? The analog sections are deigned with either nMOS or NPN transistors.

My concern is that the foundry documentation specifies a Vdd of 1.2 V. If this applies to transistors in the analog section, then the supply headroom is very limited and makes performance objectives difficult to meet.

Thanks.

Re: Maximum Vdd in BiCMOS Processes

You've probably selected a process with a min. structure size of 130nm or 90nm or below. If you want to use a Vdd > 1.2V, either use a process with larger min. structure size, or a process which additionally provides a thick oxide option for larger Vdd usage.

Re: Maximum Vdd in BiCMOS Processes

I believe Vdd in this context is the positive supply voltage, independent of the transistor type.

Re: Maximum Vdd in BiCMOS Processes

erikl said:

You've probably selected a process with a min. structure size of 130nm or 90nm or below. If you want to use a Vdd > 1.2V, either use a process with larger min. structure size, or a process which additionally provides a thick oxide option for larger Vdd usage.

Click to expand...

The minimum feature size is 130 nm. Vdd by its name means the postive supply voltage for a MOS transistor. So for the MOS transistors, I agreee, there are thick oxide devices that can operate with a higher Vdd.

However, how about the NPN devices? Would it be possible for me to use a postive supply voltage of say 1.8 V in the analog section? According to the breakdown voltages , it should be possible.

Re: Maximum Vdd in BiCMOS Processes

rreddy said:

... how about the NPN devices? Would it be possible for me to use a postive supply voltage of say 1.8 V in the analog section? According to the breakdown voltages , it should be possible.

Click to expand...

If your PDK doc. states this, you can use 1.8V for the NPNs.

Re: Maximum Vdd in BiCMOS Processes

erikl said:

If your PDK doc. states this, you can use 1.8V for the NPNs.

Click to expand...

The PDK states a Vdd = 1.2 V for the general CMOS process. For the NPN devices, only the breakdown voltages are given, i.e. no specific Vcc is given.

Perhaps other PDK's specify this directly. Its unclear if any supply voltage that does not exceed breakdown limits in the analog NPN sections can be used or is this also limited to 1.2 V.

Re: Maximum Vdd in BiCMOS Processes

rreddy said:

Its unclear if any supply voltage that does not exceed breakdown limits in the analog NPN sections can be used or is this also limited to 1.2 V.

Click to expand...

No; any supply voltage that does not exceed breakdown limits in the analog NPN sections can be used.
And for the interface to CMOS use the thick oxide devices.

Re: Maximum Vdd in BiCMOS Processes

erikl said:

No; any supply voltage that does not exceed breakdown limits in the analog NPN sections can be used.
And for the interface to CMOS use the thick oxide devices.

Click to expand...

Eureka, I understand. Thanks.