rreddy
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Hi, I am unclear on what the meaning of "Maximum Vdd" and "Vdd" in mixed signal design with BiCMOS processes. I am designing a DAC that has both digital and analog sections. My question may be split into the the digital and analog sections.
1. What does Vdd mean for digital sections? The digital sections are typically deigned with nMOS transistors.
2. What does Vdd mean for analog sections? The analog sections are deigned with either nMOS or NPN transistors.
My concern is that the foundry documentation specifies a Vdd of 1.2 V. If this applies to transistors in the analog section, then the supply headroom is very limited and makes performance objectives difficult to meet.
Thanks.
1. What does Vdd mean for digital sections? The digital sections are typically deigned with nMOS transistors.
2. What does Vdd mean for analog sections? The analog sections are deigned with either nMOS or NPN transistors.
My concern is that the foundry documentation specifies a Vdd of 1.2 V. If this applies to transistors in the analog section, then the supply headroom is very limited and makes performance objectives difficult to meet.
Thanks.