[moved] Instrumentation amplifier

I want to made instrumentation amplifier from 3 Two stage MOS Op amp which i have designes in Tanner EDA on 0.18 um TSMC process ..........i am connectin Op amps as shown in books through resistors but i dont know what of resistors is working on my designed circuit and how to apply Vcm and inputs to IA to get desired gain.......i am in gr8 trouble plz help if possible send me schematic of IA so that i can connect correctly....?

FARRUKHKHAN said:

how to apply Vcm and inputs to IA to get desired gain

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What is your Vcc,desired gain etc... ?
Can you post your circuit as well to know with which resistors you are facing problem

rahdirs said:

What is your Vcc,desired gain etc... ?
Can you post your circuit as well to know with which resistors you are facing problem

Click to expand...

Sir i dont know how to apply baising for Differential MOS pairs.....how to connect Inputs and ...and how to calculate vaules of resistances................my Vdd is 1.8 v and two stage open loop gain is 69 db
i am using TSMC 180nm process

Hi FARRUKHKHAN,

The problem with the resistances is that with smaller values you will end up loading the output stage of your Op-Amps.

In your case, the current through the resistor Resistor_2 is (Vin₊ - Vin_-)/100.
Now the question is whether the Opamp can supply this much current at all values of Vin?

The resistances that you use have to be of the value where it doesn't change the bias regions of your Op-Amp by much.
Or you can design the Op-Amp to have a larger current drive in its 2nd stage and then use smaller resistors.

nitishn5 said:

Hi FARRUKHKHAN,

The problem with the resistances is that with smaller values you will end up loading the output stage of your Op-Amps.

In your case, the current through the resistor Resistor_2 is (Vin₊ - Vin_-)/100.
Now the question is whether the Opamp can supply this much current at all values of Vin?

The resistances that you use have to be of the value where it doesn't change the bias regions of your Op-Amp by much.
Or you can design the Op-Amp to have a larger current drive in its 2nd stage and then use smaller resistors.

Click to expand...

Hi Nitish,
Can you plz send me the procedure to calculate W/L ration of MOS for Two stage MOS Op amp using gm/Id method using Tanner EDA...............i had searched alot but fing only in cadence not in Tanner but i dont have cadence so plz help

Hi FARRUKHKHAN,

I don't think the Gm/Id method is specific to Cadence. You could easily use the same thing on Tanner.

I personally do not use either Cadence or Tanner but I have still been able to design such things.

Just replace your resistors with very large value ones and try running the sim again. It should work.
But that is the easy way out.

nitishn5 said:

I don't think the Gm/Id method is specific to Cadence. You could easily use the same thing on Tanner.

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@nitishn5,

I think he means Cadence calculates W/L of MOS transistors for him.I do not use Cadence,so i don't know if it can do that.Yeah,tanner/cadence shouldn't make a difference if you can calculate yourself W/L ratios of transistors.

@FARUKHKHAN:

i did not understand your statement:"i had searched alot but fing only in cadence not in Tanner".
But,somehow from cadence you can get W/L values,use the values that you get from cadence & try those values in Tanner EDA.
Best option would be to calculate them on your own.

rahdirs said:

@nitishn5,

I think he means Cadence calculates W/L of MOS transistors for him.I do not use Cadence,so i don't know if it can do that.Yeah,tanner/cadence shouldn't make a difference if you can calculate yourself W/L ratios of transistors.

@FARUKHKHAN:

i did not understand your statement:"i had searched alot but fing only in cadence not in Tanner".
But,somehow from cadence you can get W/L values,use the values that you get from cadence & try those values in Tanner EDA.
Best option would be to calculate them on your own.

Click to expand...

I am unable to get the curves which shows in gm/Id mehtodology in Tanner i had searched in google for such curves but i got the procedure only for Cadence ..............so i just ask how to get the curves which are used in gm/id method

can any one plz tell me how to determine the value of resistances that are used in 3 Op - Amp Instrumentation amplifer as every book said that gain of instrumentation amplifier can be varied by varying resistors but i dont know how to start means what value i can take for my instrumentation how to start with resistors values ......if i am following the output equation of Instrumentation amplifer then there are many combinations of gain for several value of resistances .......what value of resistance i take to calculate the gain .........plz help

@ FARRUKHKHAN

First of all, any circuit method is independent of what simulation tool you use. All the tools are more or less the same with similar features. What you can get in one tool is quite possible in another tool.

The file you attached is also has nothing much to do with Cadence. And it clearly tells us what to simulate and what to plot.

Perhaps your understanding of MOS design and simulation is not enough. Maybe you could try simulating and plotting some basic curves such as Id vs. Vgs, or Id vs. Vds etc. and then move onto more complex stuff like gm/Id.



Second of all, regarding the Resistor values, I have already answered it before, but here it is again.
Since the resistor you use will be loading the output of the Op-amps, you need to use resistors which are large enough such that the Op-Amp is still biased correctly. You could start with a resistor larger than the output impedance of the Op-amp and than try making it smaller.