[Moved]: how to write FINFET code in Hspice????

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Re: how to write FINFET code in Hspice????

Do you need a FINFET model? If so, for which process?

The rest of any code (analysis, test bench) is the same as for a "normal" MOSFET.
 
Re: how to write FINFET code in Hspice????

thanks for reply
yeah i need FINFET model for any technology model.
please can you send netlist for simple inverter.
I want to design FINFET in HSpice.
 


Re: how to write FINFET code in Hspice????

i understand that thank you very much
Even though i got one more doubt i.e FINFET is having is more than one gate
in CMOS we use(D,S,G,B) for FINFET like this we have to go(D,S,G1,G2,B) or is there any changes.
 

Re: how to write FINFET code in Hspice????

okay thanks

For other circuits like SRAM or any other how to write spice code if we use two gates ???
FINFET is operated by two gates normally. If we connect two gates together it makes any difference than CMOS because it operates on single gate.
 

Re: how to write FINFET code in Hspice????

hii

i undertsand the concept but the problem for me is to write spice code by using two gates of a device.


i wrote code like this
Code: 
.param g2=0    ***GAte2 of pfet***
.param g4=0    ***Gate2 of nfet***

***assigned zero as the  back gate voltage for both transistors****

inv_1 out vdd vin g2 vdd pfet
inv_2 out gnd vin g4 gnd nfet

Voltage1 vdd gnd  DC 1.0 
Voltage2 vin gnd  PULSE(0 1.0 0 1n 1n 25n 75n)  

.PRINT TRAN V(vout)
.PRINT TRAN V(vin)

.tran 10n 200n
.end
**error** no definition for 0:vin
it was called by 0:inv_1

this is the error i'm getting
how to get rid of this
 
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Re: how to write FINFET code in Hspice????

Try this:

1. G1 shorted to G2
2. gnd connected to node 0 (necessary)

Hope your FinFET models are pfet and nfet, and their nodes are declared in this order:
D S G1 G2 B

PHP: 
* .param g2=0    ***Gate2 of pfet***
* .param g4=0    ***Gate2 of nfet***

***assigned zero as the  back gate voltage for both transistors****

*    D   S  G1  G2   B  model
M_1 out vdd vin vin vdd pfet
M_2 out gnd vin vin gnd nfet

Voltage1 vdd gnd  DC 1.0 
Voltage2 vin gnd  PULSE(0 1.0 0 1n 1n 25n 75n)
Vgnd     gnd  0   DC 0

.PRINT TRAN V(vout)
.PRINT TRAN V(vin)

.tran 10n 200n
.end
 
Last edited:
Re: how to write FINFET code in Hspice????

great, i tried that it's worked.

i'm getting one more error

**error** model name pmos in the element 0:m_1
is not defined.


I'm using PTM 16nm technology library to simulate the design

Code: 
** PTM-MG 16nm HSPICE Model Card for HP PFET 
** Nominal VDD=0.85V

.model pfet pmos level = 72 
+ bulkmod = 1 
+lmin    = 1e-008          lmax    = 3e-008        

** PTM-MG 16nm HSPICE Model Card for HP NFET
** Nominal VDD=0.85V

.model nfet nmos level = 72 
+ bulkmod = 1 
+lmin    = 1e-008          lmax    = 3e-008
 
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Re: how to write FINFET code in Hspice????

sainadh said:
**error** model name pmos in the element 0:m_1
is not defined.
Click to expand...

Your pfet model refers to a pmos model level = 72
(and nfet model refers to a nmos model level = 72)

... so you need to
.INCLUDE ...
Click to expand...
... these models. If you don't have them already, you'll probably find these modelcards somewhere in the BSIM-CMG, Latest Release section.

Download the .zip file, unzip and search for the modelcards. The same directory also contains sample HSPICE netlists for various analysis setUps (.sp files)
 

Re: how to write FINFET code in Hspice????

hello
i want simulate FINFET INV
what is netlist for it??
please help me???
Code: 
*inv fin
* .param g2=0    ***Gate2 of pfet***
* .param g4=0    ***Gate2 of nfet***

***assigned zero as the  back gate voltage for both transistors****

*    D   S  G1  G2   B  model
M_1 out vdd vin vin vdd pfet
M_2 out gnd vin vin gnd nfet

Voltage1 vdd gnd  DC 1.0 
Voltage2 vin gnd  PULSE(0 1.0 0 1n 1n 25n 75n)
Vgnd     gnd  0   DC 0

.PRINT TRAN V(vout)
.PRINT TRAN V(vin)

.tran 10n 200n
.end
i have a lot error
please help me
 

Re: how to write FINFET code in Hspice????

hello
1)i want simulate sram finfet but in ptm there are 32nm finfet for subcircuite but i dont want simulate sub circuite what i do??
2) for sram netlist for sizing finfet i must for pulldown transistor 3fin for pull up 1fin and for access 2fin????
thanks
 

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