seamoss
Junior Member level 3
I was looking at simple way to find Vt of a NMOS transistor, I figured, I could apply vdd on the gate and vdd on the drain and see the source dc level. So whatever the source dc level minus vdd is the Vt of the cell. Am I doing something wrong here ?
Just to cross check, I did a DC simulation applying vdd/2 on drain, sweeping Vgate and plotting the current, now I see a different Vt at which the transistor starts to conduct. Why do I See two different Vts for two different types of simulation ?
Just to cross check, I did a DC simulation applying vdd/2 on drain, sweeping Vgate and plotting the current, now I see a different Vt at which the transistor starts to conduct. Why do I See two different Vts for two different types of simulation ?