[Moved] How to count the clock and repeat the process?

sharath666 said:

Use the "forever" verilog construct...

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haseena said:

Hi
I want to know, how to count the clock pulse and for first 20 cycles it must go high and for next 20 cycles it should go low. Also, this process must repeat like a loop. I want the verilog code/program to execute in spartan 3aN. Iam new to this verilog, and i need your help. thank you in advance

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haseena said:

But "forever" keyword can be used if we know the timing of 20 cycles? without using timing units or delays how i should repeat the process? In my code i used "repeat" keyword. I will give you my code here for a reference., so that you can get some idea.thank you in advance sir.

module SQU_WAVE(output reg q,input clk);
reg [7:0] count=0;
always@(posedge clk)
repeat(10)
begin
count=count+1;
if(clk)
q=1;
else
q=0;
end
endmodule

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2. Posted in wrong forum (ASIC) should be in FPGA (Xilinx Spartan 3AN)

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ads-ee said:

1. Poor problem description, must make many assumptions on what you are really trying to accomplish
2. Posted in wrong forum (ASIC) should be in FPGA (Xilinx Spartan 3AN)
3. Asking for code, without showing that you've made any effort.
4. At least you gave a polite thanks.


1. Ah, now we get to see code.
2. This isn't synthesizable Verilog code.
3. Still don't know exactly what you want to accomplish, would have to make many assumptions to give any meaningful help.
4. Should read: http://www.catb.org/~esr/faqs/smart-questions.html so you know how to ask questions the "right" way.

As a complete guess, assuming you have a clock clk that is used to count out the timing of the 20 cycles high and 20 cycles low...
1. create a 6-bit counter that rolls over at a count equal to 39
2. for any count less than 20 output high on q
3. for any count greater than 19 output low on q
4. write code.
5. run simulation.
6. hand in working homework

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