gnvelkumar
Newbie level 4
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- May 4, 2013
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I am Velkumar, completed M.E VLSI Design in RMK Engineering College, Chennai. and secured First mark in M.E with aggregate of 8.8 CGPA. I have worked in DRDO as a trainee for SATA IP Core Development using Verilog HDL.
I have hands on experience in EDA tools such as Cadence- Virtuoso, RTL Compiler, SOC Encounter, MenterGraphics- Eldo SPICE, IC Station, Leonardospectrum, Synopsys-Tetramax, Design Vision, HSPICE.
I have worked on 180nm , 65nm technologies of TSMC, UCM foundries. It would be really helpful if you can refer me for any openings in your company
I have hands on experience in EDA tools such as Cadence- Virtuoso, RTL Compiler, SOC Encounter, MenterGraphics- Eldo SPICE, IC Station, Leonardospectrum, Synopsys-Tetramax, Design Vision, HSPICE.
I have worked on 180nm , 65nm technologies of TSMC, UCM foundries. It would be really helpful if you can refer me for any openings in your company