[moved] Error debugging in vhdl

Thread starter Ponmalar21
Start date Jun 4, 2015

Status: Not open for further replies.

Jun 4, 2015

Ponmalar21

Newbie level 4

Debug the error in the following verilog code:

Code Verilog - [expand]
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module ring_count(q,clk,clr); 
  input clk,clr; 
  output [3:0]q; 
  reg [3:0]q; 
  always @(posedge clk) 
      if(clr==1) 
            q<=4′b1000; 
        else 
            begin 
                q[3]<=q[0]; 
                q[2]<=q[3]; 
                q[1]<=q[2]; 
                q[0]<=q[1]; 
            end 
endmodule

Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15	module ring_count(q,clk,clr); input clk,clr; output [3:0]q; reg [3:0]q; always @(posedge clk) if(clr==1) q<=4′b1000; else begin q[3]<=q[0]; q[2]<=q[3]; q[1]<=q[2]; q[0]<=q[1]; end endmodule

Last edited by a moderator: Jun 4, 2015

Status: Not open for further replies.

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[moved] Error debugging in vhdl

Ponmalar21

Newbie level 4

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