Hi all,
As a novice analog IC designer, I'm working on a simple differential OTA with an active PMOS current mirror load. I'm uncertain about the output swing. Specifically, should I aim to set the output common mode DC voltage (Q point) at Vdd/2? Or should I focus primarily on other specifications like UGF, gain, and slew rate, and then adjust the Q point as needed by introducing a small differential dc voltage at the input? What is the typical approach used in the design process?
For example for vdd = 1.5v after designing my OTA let's say the output Q point is at 1.3v, which is very high, if i want it to be ~ 0.7-0.8 v can i refer back the offset to the input and adjust it from there, I know it will remove the symmetricity between the two sides of the OTA...
Please share your thoughts! Thanks in advance!!!