[MOVED] differential OTA design procedure

[Natol]

Hi all,

As a novice analog IC designer, I'm working on a simple differential OTA with an active PMOS current mirror load. I'm uncertain about the output swing. Specifically, should I aim to set the output common mode DC voltage (Q point) at Vdd/2? Or should I focus primarily on other specifications like UGF, gain, and slew rate, and then adjust the Q point as needed by introducing a small differential dc voltage at the input? What is the typical approach used in the design process?

For example for vdd = 1.5v after designing my OTA let's say the output Q point is at 1.3v, which is very high, if i want it to be ~ 0.7-0.8 v can i refer back the offset to the input and adjust it from there, I know it will remove the symmetricity between the two sides of the OTA...

Please share your thoughts! Thanks in advance!!!

 

[KlausST]

As a novice analog IC designer,

.. why didn´t you post in the "Analog Integrated Circuit (IC) Design" section then?

You are not alone posting in the wrong section....
To avoid this I asked for a more clear description of the forum sections, but no avail.

Klaus

 

[Natol]

.. why didn´t you post in the "Analog Integrated Circuit (IC) Design" section then?

You are not alone posting in the wrong section....
To avoid this I asked for a more clear description of the forum sections, but no avail.

Klaus

The question pertains to general analog circuit design, which could be relevant in both sections. If such questions are not typically addressed in this section, what types of questions are more appropriate for the "Analog Circuit Design" section?

 

[BradtheRad]

Some of us remember advice back to early years urging that we give op amps a bipolar supply (positive rail and negative rail). Notice about the early 741, that its output could not get within 2V of the negative rail. The bipolar supply makes your life easier if your input signal remains close to the 0V centerline (ground). You can easily adjust the negative rail to provide zero output from zero input.

There's nothing wrong with using a single-ended supply although you need to stay aware of your desired midway voltage at all times.

We'll see the direction this discussion leans regarding what section is appropriate. Is your next step to build this OTA into an IC?

 

[KlausST]

The question pertains to general analog circuit design

The one section is for PCB level design, using ready to buy parts. You use OPAMPs, transistors, resistors, baught from a vendor, and each device comes with a datasheet.
It´s still rather unusual to do analog designs with baught devices running on VDD of 1.5V. But possible.

Where the "Analog Integrated Circuit (IC) design"is for IC level design.
Here you use OTAs, design your own transistor based current mirrors .. on an IC / chip / silicone level.

But If you think it belongs not the the IC design section. ... I don´t want to bother you anymore.

Kaus

 

[Natol]

Some of us remember advice back to early years urging that we give op amps a bipolar supply (positive rail and negative rail). Notice about the early 741, that its output could not get within 2V of the negative rail. The bipolar supply makes your life easier if your input signal remains close to the 0V centerline (ground). You can easily adjust the negative rail to provide zero output from zero input.

There's nothing wrong with using a single-ended supply although you need to stay aware of your desired midway voltage at all times.

We'll see the direction this discussion leans regarding what section is appropriate. Is your next step to build this OTA into an IC?

Thank you for your reply! I am currently designing a CMOS based IC using the SkyWater130 pdk, so when I design a simple OTA. My first goal is to reduce the mismatch and noise effects of the active PMOS current mirror load while adhering to the bandwidth and slew rate specifications for the differential pair, and also gain etc. However, I find that when I try to meet all these specifications, the output does not consistently align with the desired midpoint.

My question is whether I can introduce a dc offset voltage at the differential pair inputs to adjust the output to be perfectly centered, without changing any of the circuit components. Is this practice advisable?

 

[BradtheRad]

Output is tapped between the right-hand totem pole. Imagine the mosfets as forming a resistive divider. Current flows through those transistors. Can you create ohm values in those transistors so as to make the voltage proportions achieve what you're asking?

Suppose you want output to equal 1/2 Vsupply. Can you make the mosfets adopt identical ohm values? It probably requires inputs to equal a particular voltage. Don't leave the inputs unconnected.

Eventually you should remove the current source at the bottom. I have a hunch it conceals a negative voltage supply. You speak as though you want a single-ended power supply with 0V gnd.

 

[Natol]

Can you create ohm values in those transistors so as to make the voltage proportions achieve what you're asking?

I understand that it's possible to adjust the output MOSFETs to operate at the midpoint, but this DC operating point is often not optimized for minimizing noise and mismatch in the PMOS current mirror. My question is whether, in my efforts to minimize these issues in the OTA, I might end up with a DC common mode at the output that isn’t centered. Would it be valid or practical to add a very small DC offset voltage at the input to adjust the output to the midpoint?

Additionally, I'm working with a single-ended power supply with a 0V ground.

 

[BradtheRad]

You can introduce a small bias voltage at the input with the option to mix that via resistor network with a different signal. However this might get to be a case where solving one problem creates another problem. Trying to solve the second problem creates a third problem.... Etc.

The reason is that real transistors don't match in every parameter. When we're running simulations it's easy to make things happen the same as textbooks. However to build a real differential detector we might need to match two hfe, two ranges of bias response, then troubleshoot more things, then more things, etc.

By the way I'm not sure you want to put a current mirror where it is now. It can defeat the principle of the differential detector. The true idea is that either left or right-hand column runs less (or more) Amperes than the other column. The total of the two columns adds up to the same amount going through the tail resistor (or transistor). That current is not supposed to change.

 

[FvM]

I understand that it's possible to adjust the output MOSFETs to operate at the midpoint, but this DC operating point is often not optimized for minimizing noise and mismatch in the PMOS current mirror. My question is whether, in my efforts to minimize these issues in the OTA, I might end up with a DC common mode at the output that isn’t centered. Would it be valid or practical to add a very small DC offset voltage at the input to adjust the output to the midpoint?

As discussed in analog design textbooks, e.g. Razavi, Design of Analog CMOS Integrated Circuits, output voltage of the discussed circuit for Vin1=Vin2 and ideally matched transistors is Vout = Vf = Vdd - |Vgs3|, due to transistor output resistance.

To shift Vout to a lower bias point, e.g. Vdd/2, you need to introduce either an intentional asymmetry in transistor areas or apply an input offset voltage. If used as amplifier, OTAs are rarely operated in open loop, thus overall feedback will set the required differential input voltage for intended output operation point. This is also necessary because real integrated circuits always involve some transistor mismatch and precalculated operation points won't work for open loop operation.

As a side remark, the term common mode voltage is inappropriate in this context, it only only applies to differential signals, e.g. output of a fully differential amplifier.

 

[Natol]

Thank you both, guys! I gained some valuable insights.

As a side remark, the term common mode voltage is inappropriate in this context, it only only applies to differential signals, e.g. output of a fully differential amplifier.

Noted, thanks!