Uh, you must never have worked on old wire wrap boards. Techs that like to route everything neat and clean were the ones you avoided wire wrapping your board, those lazy ones that just made the board an ugly mess of crisscrossing wires were the ones you lined up for!
I can assure you, I quite familiar with wire wrap boards and wire wrapping techniques after decades of using them to construct countless boards. I still have, in fact, stacks of wire wrap protoboards of all shapes, sizes and bus patterns. I also still have dozens of wire wrapping tools, both manual and electric and bins full of precut and trimmed wire.
Fortunately, those days appear to be over.
Running clock lines parallel with your data lines will allow the aggressor wire to generate noise on the victim if the aggressor signal has fast edge rates and/or large voltage swings (think old 5V 74LS logic). Of course if everything is under a couple of inches you won't have any issue and clean routing is probably easier to debug and build.
While, my choice of the term "cross" was not well chosen, I was simply attempting to convey the importance of keeping the signal lines as short as possible forming a point to point connection, rather than allowing them to meander around the design co-mingling and perhaps generating crosstalk with numerous other signal lines. Also, as I'm familiar with the Nokia 5110/PCD8544 LCD display, I realize the SPI SCLK line is typically located at the far end of the header next to the backlight, therefore if this order is maintained it would minimize the possibility of crosstalk affecting other signal lines.
I've learned from my decades of wire wrapping, that the bird's nest of leads were far from immune to crosstalk and when it became an issue, as it often did, troubleshooting and correcting the problem could be literally a nightmare, of troubleshooting to determine the culprit(s) and detaching numerous wire wrapped leads just to reroute one or more lines.
Although, the bird's nest typically formed an environment for signal line intersection, it also often provided the means for other forms of signal interference, which were typically more difficult to troubleshoot and far less pleasant to correct.
As I indicated in a previous
reply #3:
If the interface cables were of a particularly high speed, I would also recommend using every other wire as a ground line between the data and clock lines the cable was carrying.
Which are the some of the same techniques employed in many 80 conductor parallel cables used to carry both clock and data lines, for the standards like ATA-5, ATA-6, etc., at throughput rates in excess of 100MB/s.
Also, as I previously, indicated if the lengths of cable are kept to a minimum, a few centimeters, at which point the inductance and crosstalk coefficient which exists between two parallel conductors is for the most part negligible in view of the overall design requirements.
In the future, I'll attempt to choose my words more carefully.
BigDog