[moved] component instance is not fully bound digital flow design

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mehdinoormohammadi

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I am following a digital design flow in 0.18um TSMC CMOS. After synthesizing my VHDL code by Synopsis, I want to do a simulation in the gate level but I am facing with the following errors.
Code: 
 ncvhdl: 08.20-s024: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
ncvhdl: 08.20-s024: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
ncelab: 08.20-s024: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_14) [File:LIA_FSM_gate.vhd,                              Line:215].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_13) [File:LIA_FSM_gate.vhd,                              Line:216].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_12) [File:LIA_FSM_gate.vhd,                              Line:217].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_11) [File:LIA_FSM_gate.vhd,                              Line:218].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_10) [File:LIA_FSM_gate.vhd,                              Line:219].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_9) [File:LIA_FSM_gate.vhd,                              Line:220].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_reg_8) [File:LIA_FSM_gate.vhd,                              Line:221].
.
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ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_b_reg_10) [File:LIA_FSM_gate.vh                             d, Line:511].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_b_reg_11) [File:LIA_FSM_gate.vh                             d, Line:512].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_b_reg_12) [File:LIA_FSM_gate.vh                             d, Line:513].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_b_reg_13) [File:LIA_FSM_gate.vh                             d, Line:514].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:Alpha_b_reg_14) [File:LIA_FSM_gate.vh                             d, Line:515].
ncelab: *W,CUNOTB: component instance is not fully bound (:LIA_FSM_TB:uut:U148) [File:LIA_FSM_gate.vhd, Line:51                             6].
I would appreciate if you provide a solution.
 
Last edited by a moderator:

your log is not helpful at all, I have no clue what "alphareg" is.

most likely you are not including a verilog file that describes the gates.
 

Here is my VHDL code and its testbench:



Code: 
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:00:02 06/16/2017 
-- Design Name: 
-- Module Name:    LIA_FSM - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LIA_FSM is

port(clk: in std_logic;
      rst: in std_logic;
        up: in std_logic;
        dn: in std_logic;
        PhaseMUX : inout std_logic_vector(9 downto 0);
        PhaseMUX_b: inout std_logic_vector(9 downto 0);
        Alpha: inout std_logic_vector(14 downto 0);
        Alpha_b: inout std_logic_vector(14 downto 0)
        );
end LIA_FSM;

architecture LIA_FSM_arch of LIA_FSM is


--    constant limit_low : std_logic_vector (1 downto 0):="01";
--    constant limit_high : std_logic_vector (7 downto 0):="10011111";
    
begin

        process (clk)
        
           variable CNT:std_logic_vector(7 downto 0):="00000000";
            variable MSB_CNT: std_logic_vector (3 downto 0):="0000";
            variable LSB_CNT: std_logic_vector (3 downto 0):= "0000";
            
        begin
        
        
            if rising_edge(clk) then 
                


             if (rst='0') then
                
                
                if up = '1' then
                    CNT:= unsigned (CNT)+1;
                    end if;
                if dn = '1' then
                    CNT:= unsigned (CNT)-1;
                    end if;
                if (CNT< "00000001") then
                    CNT:= "10011111";
                    end if;
                if (CNT> "10011111") then
                    CNT:= "00000001";
                    end if;
--                else
--                    CNT:= "00000001";                    
                    end if;
                    
                if (rst='1') then    
                    CNT:= "00000001";    
                end if;
            
                    
                LSB_CNT:= CNT (3 downto 0);
                MSB_CNT:= CNT (7 downto 4);
                
                case LSB_CNT is
                    when "0000" =>
                        Alpha <= "000000000000000";
                        Alpha_b <= not (Alpha);
                        
                        when "0001" =>
                        Alpha <= "000000000000001";
                        Alpha_b <= not (Alpha);
                        
                        when "0010" =>
                        Alpha <= "000000000000011";
                        Alpha_b <= not (Alpha);
                        
                        when "0011" =>
                        Alpha <= "000000000000111";
                        Alpha_b <= not (Alpha);
                        
                        when "0100" =>
                        Alpha <= "000000000001111";
                        Alpha_b <= not (Alpha);
                        
                        when "0101" =>
                        Alpha <= "000000000011111";
                        Alpha_b <= not (Alpha);
                        
                        when "0110" =>
                        Alpha <= "000000000111111";
                        Alpha_b <= not (Alpha);
                        
                        when "0111" =>
                        Alpha <= "000000001111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1000" =>
                        Alpha <= "000000011111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1001" =>
                        Alpha <= "000000111111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1010" =>
                        Alpha <= "000001111111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1011" =>
                        Alpha <= "000011111111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1100" =>
                        Alpha <= "000111111111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1101" =>
                        Alpha <= "001111111111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1110" =>
                        Alpha <= "011111111111111";
                        Alpha_b <= not (Alpha);
                        
                        when "1111" =>
                        Alpha <= "111111111111111";
                        Alpha_b <= not (Alpha);
                    
                     when others =>
                    Alpha <= "000000000000000";
                        Alpha_b <= not (Alpha);
                    end case;
                
                
                
                case MSB_CNT is
                    when "0000" =>
                        PhaseMUX <= "0000000001";
                        PhaseMUX_b <= "1111111110";
                        
                        when "0001" =>
                        PhaseMUX <= "0000000010";
                        PhaseMUX_b <= "1111111101";
                        
                        when "0010" =>
                        PhaseMUX <= "0000000100";
                        PhaseMUX_b <= "1111111011";
                        
                        when "0011" =>
                        PhaseMUX <= "0000001000";
                        PhaseMUX_b <= "1111110111";
                    
                        when "0100" =>
                        PhaseMUX <= "0000010000";
                        PhaseMUX_b <= "1111101111";
                        
                        when "0101" =>
                        PhaseMUX <= "0000100000";
                        PhaseMUX_b <= "1111011111";
                    
                        when "0110" =>
                        PhaseMUX <= "0001000000";
                        PhaseMUX_b <= "1110111111";
                        
                        when "0111" =>
                        PhaseMUX <= "0010000000";
                        PhaseMUX_b <= "1101111111";
                        
                        when "1000" =>
                        PhaseMUX <= "0100000000";
                        PhaseMUX_b <= "1011111111";
                        
                        when "1001" =>
                        PhaseMUX <= "1000000000";
                        PhaseMUX_b <= "0111111111";
                    
                       when others =>
                    PhaseMUX <= "0000000001";
                        PhaseMUX_b <= "1111111110";
                    end case;
                
            end if;
            
        end process;

end LIA_FSM_arch;



Code: 
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:16:27 06/16/2017
-- Design Name:   
-- Module Name:   U:/Phd_Materials/Cadence_Simulation_Layouts/Simulation_ASIC/ISE/LIA_FSM/LIA_FSM_TB.vhd
-- Project Name:  LIA_FSM
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: LIA_FSM
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY LIA_FSM_TB IS
END LIA_FSM_TB;
 
ARCHITECTURE LIA_FSM_TB_arch OF LIA_FSM_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT LIA_FSM
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         up : IN  std_logic;
         dn : IN  std_logic;
         PhaseMUX : inout  std_logic_vector(9 downto 0);
         PhaseMUX_b : inout  std_logic_vector(9 downto 0);
         Alpha : inout  std_logic_vector(14 downto 0);
         Alpha_b : inout  std_logic_vector(14 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal up : std_logic := '0';
   signal dn : std_logic := '0';

     --Outputs
   signal PhaseMUX : std_logic_vector(9 downto 0);
   signal PhaseMUX_b : std_logic_vector(9 downto 0);
   signal Alpha : std_logic_vector(14 downto 0);
   signal Alpha_b : std_logic_vector(14 downto 0);
    

   -- Clock period definitions
   constant clk_period : time := 20 us;
    constant rst_period : time := 50 ms;
    constant up_period : time := 20 ms;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: LIA_FSM PORT MAP (
          clk => clk,
          rst => rst,
          up => up,
          dn => dn,
          PhaseMUX => PhaseMUX,
          PhaseMUX_b => PhaseMUX_b,
          Alpha => Alpha,
          Alpha_b => Alpha_b
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
    
    rst_process :process
   begin
        rst <= '1';
        wait for rst_period/(2*10);
        rst <= '0';
        wait for rst_period/2;
   end process;
 
 
 up_process :process
   begin
        up <= '1';
        wait for up_period/2;
        up <= '0';
        wait for up_period/2;
   end process;
    
    
    dn_process :process
   begin
        dn <= '0';
        wait for up_period/2;
        dn <= '1';
        wait for up_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;    

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END LIA_FSM_TB_arch;
 
Last edited by a moderator:

I don't get it. Are you doing behavioral or gate-level simulation? If you can't get the behavioral to work, you are clearly instantiating things incorrectly.
 

ThisIsNotSam said:
I don't get it. Are you doing behavioral or gate-level simulation? If you can't get the behavioral to work, you are clearly instantiating things incorrectly.
Click to expand...



I have already done the behavioral simulation and there is no problem. I am at the gate level step (the code is synthesized by Synopsis) and I get stuck in this step.
 

mehdinoormohammadi said:
I have already done the behavioral simulation and there is no problem. I am at the gate level step (the code is synthesized by Synopsis) and I get stuck in this step.
Click to expand...

So do you understand now why posting the behavioral code is pointless? I am afraid you don't understand the difference between these two.
 

ThisIsNotSam said:
So do you understand now why posting the behavioral code is pointless? I am afraid you don't understand the difference between these two.
Click to expand...


Here is my synthesized code (gate level code):


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library IEEE,tpz973g,prim;
 
use IEEE.std_logic_1164.all;
use tpz973g.all;
use prim.all;
 
package CONV_PACK_LIA_FSM is
 
-- define attributes
attribute ENUM_ENCODING : STRING;
 
end CONV_PACK_LIA_FSM;
 
library IEEE,tpz973g,prim;
 
use IEEE.std_logic_1164.all;
use tpz973g.all;
use prim.all;
 
use work.CONV_PACK_LIA_FSM.all;
 
entity LIA_FSM is
 
   port( clk, rst, up, dn : in std_logic;  PhaseMUX, PhaseMUX_b : out 
         std_logic_vector (9 downto 0);  Alpha, Alpha_b : out std_logic_vector 
         (14 downto 0));
 
end LIA_FSM;
 
architecture SYN_LIA_FSM_arch of LIA_FSM is
 
   component CLKINVX20
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component DFFTRXL
      port( D, RN, CK : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component DFFXL
      port( D, CK : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component INVX1
      port( A : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI21XL
      port( A0, A1, B0 : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND4X1
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND3X1
      port( A, B, C : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI21X1
      port( A0, A1, B0 : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI22X1
      port( A0, A1, B0, B1 : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI211X1
      port( A0, A1, B0, C0 : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI31X1
      port( A0, A1, A2, B0 : in std_logic;  Y : out std_logic);
   end component;
   
   component NAND2BX1
      port( AN, B : in std_logic;  Y : out std_logic);
   end component;
   
   component XOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component OAI2BB1X1
      port( A0N, A1N, B0 : in std_logic;  Y : out std_logic);
   end component;
   
   component XNOR2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AOI222X1
      port( A0, A1, B0, B1, C0, C1 : in std_logic;  Y : out std_logic);
   end component;
   
   component OR4X2
      port( A, B, C, D : in std_logic;  Y : out std_logic);
   end component;
   
   component OR2X2
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component NOR2BX1
      port( AN, B : in std_logic;  Y : out std_logic);
   end component;
   
   component AND2X1
      port( A, B : in std_logic;  Y : out std_logic);
   end component;
   
   component ADDHXL
      port( A, B : in std_logic;  CO, S : out std_logic);
   end component;
   
   component DFFX1
      port( D, CK : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component DFFTRX1
      port( D, RN, CK : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal CNT_7_port, CNT_6_port, CNT_5_port, CNT_4_port, CNT_3_port, 
      CNT_2_port, CNT_1_port, CNT_0_port, N42, N43, N44, N45, N46, N47, N48, 
      N51, N52, N53, N54, N55, N56, N57, LSB_CNT_2_port, LSB_CNT_1_port, 
      MSB_CNT_3_port, MSB_CNT_2_port, MSB_CNT_1_port, MSB_CNT_0_port, N180, 
      N181, N182, N184, N186, N187, N188, N190, N192, N194, N266, N267, N268, 
      N269, N270, N271, N272, N273, N274, N275, n19, n33, n34, n35, n36, n37, 
      n38, n39, n40, n41, n420, n430, n440, n450, n460, n470, n49, n50, n510, 
      n520, n530, n540, n550, n560, n570, n58, n59, n60, n61, n62, n63, n64, 
      n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79
      , n80, n81, n82, add_75xcarry_2_port, add_75xcarry_3_port, 
      add_75xcarry_4_port, add_75xcarry_5_port, add_75xcarry_6_port, 
      add_75xcarry_7_port, n83, n315, n313, n325, n324, n322, n323, n321, n318,
      n314, n317, n316, n320, n312, n326, n319, n99, n101, n103, n105, n107, 
      n109, n111, n113, n115, n117, n119, n121, n123, n125, n127, n129, n131, 
      n133, n135, n137, n139, n141, n143, n145, n147, n149, n151, n153, n155, 
      n157, n159, n161, n163, n165, n167, n169, n173, n174, n175, n176, n177, 
      n178, n179, n1800, n1810, n1820, n183, n1840, n185, n1860, n1870, n1880, 
      n189, n1900, n191, n1920, n193, n1940, n195, n196, n197, n198, n199, n200
      , n201, n202, n203, n204, n205, n271_port, n272_port, n273_port, 
      n274_port, n275_port, n276, n277, n278, n279, n280, n281, n282, n283, 
      n284, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, 
      n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, 
      n308, n309, n310, n311, n_1000, n_1001, n_1002 : std_logic;
 
begin
   
   CNT_reg_5 : DFFTRX1 port map( D => n83, RN => n174, CK => clk, Q => 
                           CNT_5_port, QN => n_1000);
   CNT_reg_6 : DFFTRX1 port map( D => n83, RN => n173, CK => clk, Q => 
                           CNT_6_port, QN => n_1001);
   LSB_CNT_reg_0 : DFFX1 port map( D => CNT_0_port, CK => clk, Q => n_1002, QN 
                           => n19);
   add_75xU1_1_4 : ADDHXL port map( A => CNT_4_port, B => add_75xcarry_4_port, 
                           CO => add_75xcarry_5_port, S => N45);
   add_75xU1_1_3 : ADDHXL port map( A => CNT_3_port, B => add_75xcarry_3_port, 
                           CO => add_75xcarry_4_port, S => N44);
   add_75xU1_1_2 : ADDHXL port map( A => CNT_2_port, B => add_75xcarry_2_port, 
                           CO => add_75xcarry_3_port, S => N43);
   add_75xU1_1_5 : ADDHXL port map( A => CNT_5_port, B => add_75xcarry_5_port, 
                           CO => add_75xcarry_6_port, S => N46);
   add_75xU1_1_1 : ADDHXL port map( A => CNT_1_port, B => CNT_0_port, CO => 
                           add_75xcarry_2_port, S => N42);
   add_75xU1_1_6 : ADDHXL port map( A => CNT_6_port, B => add_75xcarry_6_port, 
                           CO => add_75xcarry_7_port, S => N47);
   xcellx1887 : AND2X1 port map( A => n69, B => n193, Y => n169);
   LSB_CNT_reg_1 : DFFXL port map( D => CNT_1_port, CK => clk, Q => 
                           LSB_CNT_1_port, QN => n183);
   U82 : OR2X2 port map( A => n204, B => n203, Y => n83);
   U99 : CLKINVX20 port map( A => n99, Y => Alpha_b(14));
   U101 : CLKINVX20 port map( A => n101, Y => PhaseMUX(1));
   U103 : CLKINVX20 port map( A => n103, Y => Alpha_b(10));
   U105 : CLKINVX20 port map( A => n105, Y => Alpha_b(12));
   U107 : CLKINVX20 port map( A => n107, Y => Alpha_b(8));
   U109 : CLKINVX20 port map( A => n109, Y => Alpha_b(9));
   U111 : CLKINVX20 port map( A => n111, Y => Alpha_b(6));
   U113 : CLKINVX20 port map( A => n113, Y => Alpha_b(7));
   U115 : CLKINVX20 port map( A => n115, Y => Alpha_b(4));
   U117 : CLKINVX20 port map( A => n117, Y => Alpha_b(5));
   U119 : CLKINVX20 port map( A => n119, Y => Alpha_b(2));
   U121 : CLKINVX20 port map( A => n121, Y => Alpha_b(3));
   U123 : CLKINVX20 port map( A => n123, Y => Alpha_b(0));
   U125 : CLKINVX20 port map( A => n125, Y => Alpha_b(1));
   U127 : CLKINVX20 port map( A => n127, Y => Alpha_b(11));
   U129 : CLKINVX20 port map( A => n129, Y => Alpha_b(13));
   U131 : CLKINVX20 port map( A => n131, Y => PhaseMUX_b(4));
   U133 : CLKINVX20 port map( A => n133, Y => PhaseMUX_b(6));
   U135 : CLKINVX20 port map( A => n135, Y => PhaseMUX(6));
   U137 : CLKINVX20 port map( A => n137, Y => PhaseMUX_b(2));
   U139 : CLKINVX20 port map( A => n139, Y => PhaseMUX(2));
   U141 : CLKINVX20 port map( A => n141, Y => PhaseMUX(4));
   U143 : CLKINVX20 port map( A => n143, Y => PhaseMUX(5));
   U145 : CLKINVX20 port map( A => n145, Y => PhaseMUX(7));
   U147 : CLKINVX20 port map( A => n147, Y => PhaseMUX_b(7));
   U149 : CLKINVX20 port map( A => n149, Y => PhaseMUX(3));
   U151 : CLKINVX20 port map( A => n151, Y => PhaseMUX_b(3));
   U153 : CLKINVX20 port map( A => n153, Y => PhaseMUX_b(5));
   U155 : CLKINVX20 port map( A => n155, Y => PhaseMUX_b(9));
   U157 : CLKINVX20 port map( A => n157, Y => PhaseMUX_b(1));
   U159 : CLKINVX20 port map( A => n159, Y => PhaseMUX_b(0));
   U161 : CLKINVX20 port map( A => n161, Y => PhaseMUX_b(8));
   U163 : CLKINVX20 port map( A => n163, Y => PhaseMUX(9));
   U165 : CLKINVX20 port map( A => n165, Y => PhaseMUX(8));
   U167 : CLKINVX20 port map( A => n167, Y => PhaseMUX(0));
   U168 : INVX1 port map( A => n71, Y => n193);
   U169 : NOR2BX1 port map( AN => n66, B => n175, Y => n530);
   U170 : NOR2X1 port map( A => n83, B => n65, Y => n520);
   U171 : NAND2X1 port map( A => n183, B => n76, Y => N181);
   U172 : INVX1 port map( A => n76, Y => n179);
   U173 : NAND2X1 port map( A => n1940, B => n195, Y => n71);
   U174 : NAND2X1 port map( A => n69, B => n193, Y => N267);
   U175 : INVX1 port map( A => n72, Y => n1810);
   U176 : INVX1 port map( A => n75, Y => n178);
   U177 : INVX1 port map( A => n74, Y => n177);
   U178 : INVX1 port map( A => N266, Y => n1840);
   U179 : INVX1 port map( A => N271, Y => n189);
   U180 : INVX1 port map( A => N273, Y => n1900);
   U181 : INVX1 port map( A => N269, Y => n1880);
   U182 : INVX1 port map( A => N274, Y => n191);
   U183 : INVX1 port map( A => N275, Y => n1920);
   U184 : INVX1 port map( A => N268, Y => n185);
   U185 : INVX1 port map( A => N270, Y => n1860);
   U186 : INVX1 port map( A => N272, Y => n1870);
   U187 : NOR2BX1 port map( AN => dn, B => n65, Y => n540);
   U188 : NOR2BX1 port map( AN => n66, B => up, Y => n510);
   U189 : OAI31X1 port map( A0 => n183, A1 => n1820, A2 => n19, B0 => n1800, Y 
                           => N186);
   U190 : NOR2X1 port map( A => LSB_CNT_2_port, B => N184, Y => n76);
   U191 : AOI21X1 port map( A0 => LSB_CNT_2_port, A1 => LSB_CNT_1_port, B0 => 
                           N186, Y => n75);
   U192 : OAI21XL port map( A0 => n1820, A1 => n19, B0 => n75, Y => N184);
   U193 : OR2X2 port map( A => n200, B => CNT_5_port, Y => n201);
   U194 : NAND2BX1 port map( AN => CNT_1_port, B => n176, Y => n197);
   U195 : NOR2X1 port map( A => n65, B => dn, Y => n66);
   U196 : OAI21XL port map( A0 => n19, A1 => n183, B0 => n76, Y => N182);
   U197 : OR2X2 port map( A => n197, B => CNT_2_port, Y => n198);
   U198 : OR2X2 port map( A => n198, B => CNT_3_port, Y => n199);
   U199 : OR2X2 port map( A => n199, B => CNT_4_port, Y => n200);
   U201 : OR4X2 port map( A => CNT_1_port, B => CNT_0_port, C => CNT_3_port, D 
                           => CNT_2_port, Y => n203);
   U202 : OR4X2 port map( A => CNT_5_port, B => CNT_4_port, C => CNT_7_port, D 
                           => CNT_6_port, Y => n204);
   U203 : XOR2X1 port map( A => CNT_7_port, B => n202, Y => N57);
   U204 : NOR2X1 port map( A => CNT_6_port, B => n201, Y => n202);
   U205 : INVX1 port map( A => n61, Y => n174);
   U206 : AOI222X1 port map( A0 => N55, A1 => n540, B0 => CNT_5_port, B1 => 
                           n510, C0 => N46, C1 => n530, Y => n61);
   U207 : OAI2BB1X1 port map( A0N => n200, A1N => CNT_5_port, B0 => n201, Y => 
                           N55);
   U208 : INVX1 port map( A => n62, Y => n173);
   U209 : AOI222X1 port map( A0 => N56, A1 => n540, B0 => CNT_6_port, B1 => 
                           n510, C0 => N47, C1 => n530, Y => n62);
   U210 : XNOR2X1 port map( A => CNT_6_port, B => n201, Y => N56);
   U211 : NAND2X1 port map( A => n59, B => n60, Y => n80);
   U212 : AOI22X1 port map( A0 => N45, A1 => n530, B0 => N54, B1 => n540, Y => 
                           n59);
   U213 : AOI21X1 port map( A0 => CNT_4_port, A1 => n510, B0 => n520, Y => n60)
                           ;
   U214 : OAI2BB1X1 port map( A0N => n199, A1N => CNT_4_port, B0 => n200, Y => 
                           N54);
   U215 : NAND2X1 port map( A => n570, B => n58, Y => n79);
   U216 : AOI22X1 port map( A0 => N44, A1 => n530, B0 => N53, B1 => n540, Y => 
                           n570);
   U217 : AOI21X1 port map( A0 => CNT_3_port, A1 => n510, B0 => n520, Y => n58)
                           ;
   U218 : OAI2BB1X1 port map( A0N => n198, A1N => CNT_3_port, B0 => n199, Y => 
                           N53);
   U219 : NAND2X1 port map( A => n550, B => n560, Y => n78);
   U220 : AOI22X1 port map( A0 => N43, A1 => n530, B0 => N52, B1 => n540, Y => 
                           n550);
   U221 : AOI21X1 port map( A0 => CNT_2_port, A1 => n510, B0 => n520, Y => n560
                           );
   U222 : OAI2BB1X1 port map( A0N => n197, A1N => CNT_2_port, B0 => n198, Y => 
                           N52);
   U223 : NAND2X1 port map( A => n49, B => n50, Y => n77);
   U224 : AOI22X1 port map( A0 => N42, A1 => n530, B0 => N51, B1 => n540, Y => 
                           n49);
   U225 : AOI21X1 port map( A0 => CNT_1_port, A1 => n510, B0 => n520, Y => n50)
                           ;
   U226 : OAI2BB1X1 port map( A0N => CNT_0_port, A1N => CNT_1_port, B0 => n197,
                           Y => N51);
   U227 : NAND2X1 port map( A => n63, B => n64, Y => n81);
   U228 : AOI21X1 port map( A0 => CNT_7_port, A1 => n510, B0 => n520, Y => n64)
                           ;
   U229 : AOI22X1 port map( A0 => N48, A1 => n530, B0 => N57, B1 => n540, Y => 
                           n63);
   U230 : XOR2X1 port map( A => add_75xcarry_7_port, B => CNT_7_port, Y => N48)
                           ;
   U231 : NAND2BX1 port map( AN => rst, B => n205, Y => n65);
   U232 : OAI21XL port map( A0 => CNT_6_port, A1 => CNT_5_port, B0 => 
                           CNT_7_port, Y => n205);
   U233 : OAI31X1 port map( A0 => n183, A1 => n1800, A2 => n19, B0 => n72, Y =>
                           N190);
   U234 : NOR2X1 port map( A => n196, B => MSB_CNT_3_port, Y => n69);
   U235 : NOR2X1 port map( A => MSB_CNT_3_port, B => MSB_CNT_0_port, Y => n70);
   U236 : AOI21X1 port map( A0 => N187, A1 => LSB_CNT_1_port, B0 => N190, Y => 
                           n74);
   U237 : AOI22X1 port map( A0 => n71, A1 => MSB_CNT_3_port, B0 => n193, B1 => 
                           n70, Y => N266);
   U238 : NAND2X1 port map( A => N187, B => LSB_CNT_2_port, Y => n72);
   U239 : OAI211X1 port map( A0 => dn, A1 => n67, B0 => n83, C0 => n68, Y => 
                           n82);
   U240 : AOI22X1 port map( A0 => CNT_0_port, A1 => n175, B0 => n176, B1 => up,
                           Y => n67);
   U241 : AOI21X1 port map( A0 => n176, A1 => dn, B0 => n65, Y => n68);
   U242 : NAND3X1 port map( A => n69, B => n195, C => MSB_CNT_2_port, Y => N271
                           );
   U243 : NAND3X1 port map( A => MSB_CNT_1_port, B => n69, C => MSB_CNT_2_port,
                           Y => N273);
   U244 : NAND3X1 port map( A => n69, B => n1940, C => MSB_CNT_1_port, Y => 
                           N269);
   U245 : NAND3X1 port map( A => n193, B => n196, C => MSB_CNT_3_port, Y => 
                           N274);
   U246 : NAND3X1 port map( A => MSB_CNT_0_port, B => n193, C => MSB_CNT_3_port
                           , Y => N275);
   U247 : NAND3X1 port map( A => MSB_CNT_1_port, B => n1940, C => n70, Y => 
                           N268);
   U248 : NAND3X1 port map( A => MSB_CNT_2_port, B => n195, C => n70, Y => N270
                           );
   U249 : NAND3X1 port map( A => MSB_CNT_2_port, B => MSB_CNT_1_port, C => n70,
                           Y => N272);
   U250 : NOR3X1 port map( A => n183, B => n72, C => n19, Y => N194);
   U251 : NAND4X1 port map( A => n19, B => n183, C => n1820, D => n1800, Y => 
                           N180);
   U252 : OAI21XL port map( A0 => n1800, A1 => n19, B0 => n74, Y => N188);
   U253 : OAI21XL port map( A0 => n72, A1 => n19, B0 => n73, Y => N192);
   U254 : NAND2X1 port map( A => LSB_CNT_1_port, B => n1810, Y => n73);
   U260 : INVX1 port map( A => up, Y => n175);
   LSB_CNT_reg_3 : DFFXL port map( D => CNT_3_port, CK => clk, Q => N187, QN =>
                           n1800);
   LSB_CNT_reg_2 : DFFXL port map( D => CNT_2_port, CK => clk, Q => 
                           LSB_CNT_2_port, QN => n1820);
   MSB_CNT_reg_0 : DFFXL port map( D => CNT_4_port, CK => clk, Q => 
                           MSB_CNT_0_port, QN => n196);
   MSB_CNT_reg_1 : DFFXL port map( D => CNT_5_port, CK => clk, Q => 
                           MSB_CNT_1_port, QN => n195);
   MSB_CNT_reg_3 : DFFXL port map( D => CNT_7_port, CK => clk, Q => 
                           MSB_CNT_3_port, QN => n311);
   MSB_CNT_reg_2 : DFFXL port map( D => CNT_6_port, CK => clk, Q => 
                           MSB_CNT_2_port, QN => n1940);
   Alpha_b_reg_13 : DFFXL port map( D => n34, CK => clk, Q => n310, QN => n129)
                           ;
   Alpha_b_reg_11 : DFFXL port map( D => n36, CK => clk, Q => n309, QN => n127)
                           ;
   Alpha_b_reg_14 : DFFXL port map( D => n33, CK => clk, Q => n308, QN => n99);
   Alpha_b_reg_12 : DFFXL port map( D => n35, CK => clk, Q => n307, QN => n105)
                           ;
   Alpha_b_reg_10 : DFFXL port map( D => n37, CK => clk, Q => n306, QN => n103)
                           ;
   Alpha_b_reg_9 : DFFXL port map( D => n38, CK => clk, Q => n305, QN => n109);
   Alpha_b_reg_8 : DFFXL port map( D => n39, CK => clk, Q => n304, QN => n107);
   Alpha_b_reg_7 : DFFXL port map( D => n40, CK => clk, Q => n303, QN => n113);
   Alpha_b_reg_6 : DFFXL port map( D => n41, CK => clk, Q => n302, QN => n111);
   Alpha_b_reg_5 : DFFXL port map( D => n420, CK => clk, Q => n301, QN => n117)
                           ;
   Alpha_b_reg_4 : DFFXL port map( D => n430, CK => clk, Q => n300, QN => n115)
                           ;
   Alpha_b_reg_3 : DFFXL port map( D => n440, CK => clk, Q => n299, QN => n121)
                           ;
   Alpha_b_reg_2 : DFFXL port map( D => n450, CK => clk, Q => n298, QN => n119)
                           ;
   Alpha_b_reg_1 : DFFXL port map( D => n460, CK => clk, Q => n297, QN => n125)
                           ;
   Alpha_b_reg_0 : DFFXL port map( D => n470, CK => clk, Q => n296, QN => n123)
                           ;
   PhaseMUX_b_reg_6 : DFFXL port map( D => N272, CK => clk, Q => n295, QN => 
                           n133);
   PhaseMUX_b_reg_4 : DFFXL port map( D => N270, CK => clk, Q => n294, QN => 
                           n131);
   PhaseMUX_b_reg_2 : DFFXL port map( D => N268, CK => clk, Q => n293, QN => 
                           n137);
   PhaseMUX_reg_6 : DFFXL port map( D => n1870, CK => clk, Q => n292, QN => 
                           n135);
   PhaseMUX_reg_4 : DFFXL port map( D => n1860, CK => clk, Q => n291, QN => 
                           n141);
   PhaseMUX_reg_2 : DFFXL port map( D => n185, CK => clk, Q => n290, QN => n139
                           );
   PhaseMUX_reg_7 : DFFXL port map( D => n1900, CK => clk, Q => n289, QN => 
                           n145);
   PhaseMUX_reg_5 : DFFXL port map( D => n189, CK => clk, Q => n288, QN => n143
                           );
   PhaseMUX_reg_3 : DFFXL port map( D => n1880, CK => clk, Q => n287, QN => 
                           n149);
   PhaseMUX_b_reg_7 : DFFXL port map( D => N273, CK => clk, Q => n286, QN => 
                           n147);
   PhaseMUX_b_reg_5 : DFFXL port map( D => N271, CK => clk, Q => n285, QN => 
                           n153);
   PhaseMUX_b_reg_3 : DFFXL port map( D => N269, CK => clk, Q => n284, QN => 
                           n151);
   PhaseMUX_b_reg_1 : DFFXL port map( D => N267, CK => clk, Q => n283, QN => 
                           n157);
   PhaseMUX_b_reg_9 : DFFXL port map( D => N275, CK => clk, Q => n282, QN => 
                           n155);
   PhaseMUX_b_reg_8 : DFFXL port map( D => N274, CK => clk, Q => n281, QN => 
                           n161);
   CNT_reg_0 : DFFXL port map( D => n82, CK => clk, Q => CNT_0_port, QN => n176
                           );
   PhaseMUX_b_reg_0 : DFFXL port map( D => N266, CK => clk, Q => n280, QN => 
                           n159);
   PhaseMUX_reg_8 : DFFXL port map( D => n191, CK => clk, Q => n279, QN => n165
                           );
   PhaseMUX_reg_1 : DFFXL port map( D => n169, CK => clk, Q => n278, QN => n101
                           );
   PhaseMUX_reg_9 : DFFXL port map( D => n1920, CK => clk, Q => n277, QN => 
                           n163);
   PhaseMUX_reg_0 : DFFXL port map( D => n1840, CK => clk, Q => n276, QN => 
                           n167);
   CNT_reg_4 : DFFXL port map( D => n80, CK => clk, Q => CNT_4_port, QN => 
                           n275_port);
   CNT_reg_3 : DFFXL port map( D => n79, CK => clk, Q => CNT_3_port, QN => 
                           n274_port);
   CNT_reg_2 : DFFXL port map( D => n78, CK => clk, Q => CNT_2_port, QN => 
                           n273_port);
   CNT_reg_1 : DFFXL port map( D => n77, CK => clk, Q => CNT_1_port, QN => 
                           n272_port);
   CNT_reg_7 : DFFXL port map( D => n81, CK => clk, Q => CNT_7_port, QN => 
                           n271_port);
   Alpha_buffer_reg_0 : DFFXL port map( D => N180, CK => clk, Q => n326, QN => 
                           n470);
   Alpha_buffer_reg_7 : DFFXL port map( D => N187, CK => clk, Q => n319, QN => 
                           n40);
   Alpha_buffer_reg_14 : DFFXL port map( D => N194, CK => clk, Q => n312, QN =>
                           n33);
   Alpha_buffer_reg_6 : DFFXL port map( D => N186, CK => clk, Q => n320, QN => 
                           n41);
   Alpha_buffer_reg_10 : DFFXL port map( D => N190, CK => clk, Q => n316, QN =>
                           n37);
   Alpha_buffer_reg_9 : DFFXL port map( D => n177, CK => clk, Q => n317, QN => 
                           n38);
   Alpha_buffer_reg_12 : DFFXL port map( D => N192, CK => clk, Q => n314, QN =>
                           n35);
   Alpha_buffer_reg_8 : DFFXL port map( D => N188, CK => clk, Q => n318, QN => 
                           n39);
   Alpha_buffer_reg_5 : DFFXL port map( D => n178, CK => clk, Q => n321, QN => 
                           n420);
   Alpha_buffer_reg_3 : DFFXL port map( D => n179, CK => clk, Q => n323, QN => 
                           n440);
   Alpha_buffer_reg_4 : DFFXL port map( D => N184, CK => clk, Q => n322, QN => 
                           n430);
   Alpha_buffer_reg_2 : DFFXL port map( D => N182, CK => clk, Q => n324, QN => 
                           n450);
   Alpha_buffer_reg_1 : DFFXL port map( D => N181, CK => clk, Q => n325, QN => 
                           n460);
   Alpha_buffer_reg_13 : DFFTRXL port map( D => LSB_CNT_1_port, RN => n1810, CK
                           => clk, Q => n313, QN => n34);
   Alpha_buffer_reg_11 : DFFTRXL port map( D => N187, RN => LSB_CNT_2_port, CK 
                           => clk, Q => n315, QN => n36);
   U83 : CLKINVX20 port map( A => n36, Y => Alpha(11));
   U84 : CLKINVX20 port map( A => n34, Y => Alpha(13));
   U85 : CLKINVX20 port map( A => n460, Y => Alpha(1));
   U86 : CLKINVX20 port map( A => n450, Y => Alpha(2));
   U87 : CLKINVX20 port map( A => n430, Y => Alpha(4));
   U88 : CLKINVX20 port map( A => n440, Y => Alpha(3));
   U89 : CLKINVX20 port map( A => n420, Y => Alpha(5));
   U90 : CLKINVX20 port map( A => n39, Y => Alpha(8));
   U91 : CLKINVX20 port map( A => n35, Y => Alpha(12));
   U92 : CLKINVX20 port map( A => n38, Y => Alpha(9));
   U93 : CLKINVX20 port map( A => n37, Y => Alpha(10));
   U94 : CLKINVX20 port map( A => n41, Y => Alpha(6));
   U95 : CLKINVX20 port map( A => n33, Y => Alpha(14));
   U96 : CLKINVX20 port map( A => n40, Y => Alpha(7));
   U97 : CLKINVX20 port map( A => n470, Y => Alpha(0));
 
end SYN_LIA_FSM_arch;
 


show me the command you are using to simulate this. the full command, exactly as used.
 

ThisIsNotSam said:
show me the command you are using to simulate this. the full command, exactly as used.
Click to expand...

I am using the following scripts which is inserted in Synopsis to produce the gate level VHDL (and Verilog) file:

Code: 
sh rm -Rf Work 
sh mkdir Work
define_design_lib Work -path "./Work"
analyze -format vhdl -lib WORK ../HDLs/LIA_FSM.vhd
elaborate LIA_FSM -arch "LIA_FSM_arch" -lib DEFAULT -update
set_load 5 "PhaseMUX_9_"
set_load 5 "PhaseMUX_8_"
set_load 5 "PhaseMUX_7_"
set_load 5 "PhaseMUX_6_"
set_load 5 "PhaseMUX_5_"
set_load 5 "PhaseMUX_4_"
set_load 5 "PhaseMUX_3_"
set_load 5 "PhaseMUX_2_"
set_load 5 "PhaseMUX_1_"
set_load 5 "PhaseMUX_0_"

set_load 5 "PhaseMUX_b_9_"
set_load 5 "PhaseMUX_b_8_"
set_load 5 "PhaseMUX_b_7_"
set_load 5 "PhaseMUX_b_6_"
set_load 5 "PhaseMUX_b_5_"
set_load 5 "PhaseMUX_b_4_"
set_load 5 "PhaseMUX_b_3_"
set_load 5 "PhaseMUX_b_2_"
set_load 5 "PhaseMUX_b_1_"
set_load 5 "PhaseMUX_b_0_"

set_load 5 "Alpha_14_"
set_load 5 "Alpha_13_"
set_load 5 "Alpha_12_"
set_load 5 "Alpha_11_"
set_load 5 "Alpha_10_"
set_load 5 "Alpha_9_"
set_load 5 "Alpha_8_"
set_load 5 "Alpha_7_"
set_load 5 "Alpha_6_"
set_load 5 "Alpha_5_"
set_load 5 "Alpha_4_"
set_load 5 "Alpha_3_"
set_load 5 "Alpha_2_"
set_load 5 "Alpha_1_"
set_load 5 "Alpha_0_"

set_load 5 "Alpha_b_14_"
set_load 5 "Alpha_b_13_"
set_load 5 "Alpha_b_12_"
set_load 5 "Alpha_b_11_"
set_load 5 "Alpha_b_10_"
set_load 5 "Alpha_b_9_"
set_load 5 "Alpha_b_8_"
set_load 5 "Alpha_b_7_"
set_load 5 "Alpha_b_6_"
set_load 5 "Alpha_b_5_"
set_load 5 "Alpha_b_4_"
set_load 5 "Alpha_b_3_"
set_load 5 "Alpha_b_2_"
set_load 5 "Alpha_b_1_"
set_load 5 "Alpha_b_0_"

#create_clock -name "clk" -period 10 -waveform {   "0" "5" } {   "clk" }
create_clock -name sysclock -period 10 -waveform {0 5} [get_ports clk]
set_dont_touch_network [get_ports {clk}] 
set_clock_latency -source -late -rise 0.800 [get_clocks sysclock]
set_clock_latency -source -late -fall 0.750 [get_clocks sysclock]
set_clock_latency -source -early -rise 0.500 [get_clocks sysclock]
set_clock_latency -source -early -fall 0.460 [get_clocks sysclock]
set_clock_uncertainty -setup 0.1 [get_clocks sysclock]
set_clock_uncertainty -hold 0.1 [get_clocks sysclock]
#derive_clock_uncertainty
#update_timing_netlist
#set_clock_skew -propagated clk
#set_clock_skew -plus_uncertainty 0.1 "clk"
#set_clock_skew -minus_uncertainty 0.1 "clk"
set_fix_multiple_port_nets -all
write -format ddc -hierarchy -output "LIA_FSM_constrained.ddc" 

remove_design -designs
read_ddc LIA_FSM_constrained.ddc
#current_design "LIA_FSM_constrained.ddc"
compile -ungroup_all
#current_design "LIA_FSM_constrained.ddc"
write -format ddc -hierarchy -output "LIA_FSM_compile1.ddc"
report_area
report_constraints
report_timing -path full -delay max -max_paths 1 -nworst 1
check_design

remove_design -designs
read_ddc LIA_FSM_compile1.ddc
#current_design "LIA_FSM_compile1.ddc"
compile -map_effort high -incremental_mapping
write -format ddc -hierarchy -output "LIA_FSM_compile2.ddc" 
report_area
report_constraints
report_timing -path full -delay max -max_paths 1 -nworst 1
check_design
#vhdlout_dont_create_dummy_nets = "TRUE"
change_names -hier -rule vhdl
write -f vhdl -hierarchy -output "LIA_FSM_gate.vhd" 
change_names -hier -rule verilog
write -f verilog -hierarchy -output "LIA_FSM_gate.v"

For gate level simulation I run the following script:

Code: 
#!/bin/ksh -f
ncvhdl LIA_FSM_gate.v
ncvhdl ../testbench/LIA_FSM_TB.vhd
ncelab -TIMESCALE 10ps/1ps -access +r worklib.LIA_FSM_TB:LIA_FSM_TB_arch 
ncsim -gui worklib.LIA_FSM_TB:LIA_FSM_TB_arch
#run 1800000ns
#exit
 
Last edited by a moderator:

ThisIsNotSam said:
this. you forgot the library verilog file.
Click to expand...


Synopsis produces both Verilog and VHDL. I am not sure the Verilog file is necessary to sue! only the VHDL file is ok. However, I try to runt he simulation with verilog, but I got the same error.
 

mehdinoormohammadi said:
Synopsis produces both Verilog and VHDL. I am not sure the Verilog file is necessary to sue! only the VHDL file is ok. However, I try to runt he simulation with verilog, but I got the same error.
Click to expand...

ThisIsNotSam is not talking about the netlist, you didn't include the simulation library of all the primitives that are in your netlist. Don't know about ncsim, but a lot of simulators use -L compiled_primitive_library somewhere in the compilation process, but you didn't do that anywhere in your script.
 

mehdinoormohammadi said:
Synopsis produces both Verilog and VHDL. I am not sure the Verilog file is necessary to sue! only the VHDL file is ok. However, I try to runt he simulation with verilog, but I got the same error.
Click to expand...

Your standard cell library comes with a verilog file that describes each gate in it. Find that file and all of your problems will go away.
 

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