The wave-forms look very similar to I2S bus transactions. But there is no info on whether a I2S master or slave needs to be designed. Any type of bus will have a master and as slave.
"Is it possible to write a code to FPGA based only on this and PINs arrangement?"
First question to you: The person describing this on the white-board, did he/she not tell you what logic is creating such a waveform? In order to write the HDL you need to have this info.
"What type of system does it show? (counter, register, ...?)"
It just shows the nature of a bus transaction...nothing else!
"Does in each variants there are 3 or 4 signals (what does DATA signal connected to?)"
Again you need to ask this to the person who has assigned you such a task!
"I work with Nexys™3 Spartan-6 FPGA Board."
No problem!