Re: [moved] Anyone experienced with Synplify for synthesis?
Hello,
First of all, I am using Synplify tool and not Precision!
I am posting a part of the error report file. My current problem is Synplify is not able find the VHDL libraries that are defined in some top-level blocks. I think that due to this it shows many errors.
My TCL script in which I am using a Xilinx VHDL IP:
Code:
# Open a new Project
project -new
# Set the target technology, part number, package, and speed grade options.
# some verilog files are added
# Xilinx VHDL IP
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/iic_pkg.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/dynamic_master.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/shift8.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/upcnt_n.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/iic_control.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/debounce.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/filter.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/reg_interface.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/interrupt_control.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/axi_ipif_ssp1.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/iic.vhd
add_file -vhdl $HW_TOP/src/top_modules/axi_iic_v1_02_a/axi_iic.vhd
add_file -verilog $HW_TOP/src/top_modules/axi_iic_v1_02_a/axi_iic_bi_di.v
# This is my topmodule in Verilog
add_file -verilog $HW_TOP/src/fpga/te0630_top.v
add_file -constraint te0630_top.sdc
impl -add te0630_top -type fpga
# Set top level module
set_option -top_module te0630_top
#set result format/file last
project -result_file "./te0630_top/te0630_top.edf"
project -save "te0630_top.prj"
# Synthesize the existing Project
project -run
Part of the report where errors and warnings are shown:
Code:
Synopsys VHDL Compiler, version comp201403rcp1, Build 010R, built Mar 24 2014
@N|Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N: CD720 :"/home/shared/Synopsys/I-2014.03-1/lib/vhd/std.vhd":123:18:123:21|Setting time resolution to ns
@N:"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/axi_iic.vhd":146:7:146:13|Top entity is set to axi_iic.
@W: CD642 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/interrupt_control.vhd":167:43:167:43|Ignoring use clause - library proc_common_v3_00_a not found ...
@W: CD642 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/interrupt_control.vhd":168:36:168:36|Ignoring use clause - library proc_common_v3_00_a not found ...
@E: CD255 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/interrupt_control.vhd":182:53:182:54|No identifier "integer_array_type" in scope
@E: CD255 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/interrupt_control.vhd":304:31:304:31|No identifier "log2" in scope
2 errors parsing file /home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/interrupt_control.vhd
@W: CD642 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":95:31:95:31|Ignoring use clause - library axi_iic_v1_02_a not found ...
@W: CD642 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":96:27:96:27|Ignoring use clause - library axi_iic_v1_02_a not found ...
@W: CD642 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":97:26:97:26|Ignoring use clause - library axi_iic_v1_02_a not found ...
@E: CD591 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":509:6:509:12|Object axi_iic_v1_02_a is not a library
@E: CD415 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":900:34:900:34|Expecting keyword is
@E: CD632 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":1910:39:1910:39|duplicate entity name axi_iic_v1_02_a
@E: CD632 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":2012:41:2012:41|duplicate entity name axi_iic_v1_02_a
@E: CD632 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":2044:34:2044:34|duplicate entity name axi_iic_v1_02_a
@E: CD415 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd":2079:20:2079:20|Expecting keyword of
8 errors parsing file /home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/iic_control.vhd
@E: CD418 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/filter.vhd":98:28:98:28|use: can't find work.axi_iic_v1_02_a.debounce
@E: CD255 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/filter.vhd":121:31:121:31|No identifier "std_logic" in scope
@E: CD632 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/filter.vhd":129:17:129:17|duplicate entity name filter
@E: CD632 :"/home/dpaul/nanocore/rev28462_fpga/src/top_modules/axi_iic_v1_02_a/filter.vhd":129:17:129:17|Too many errors - aborting.
# Mon May 18 10:05:52 2015
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@E::VHDL compiler failed
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon May 18 10:05:52 2015
###########################################################]
The dir structure of the VHDL IP:
Code:
-rw-rw---- 1 dpaul dpaul 761 Mai 6 14:18 axi_iic_bi_di.v
-rw-r--r-- 1 dpaul dpaul 13893 Apr 29 16:51 axi_iic.vhd
-rw-r--r-- 1 dpaul dpaul 22057 Dez 5 2012 axi_ipif_ssp1.vhd
drwxrwx--- 2 dpaul dpaul 4096 Apr 20 13:24 axi_lite_ipif_v1_01_a
-rw-r--r-- 1 dpaul dpaul 9747 Dez 5 2012 debounce.vhd
-rw-r--r-- 1 dpaul dpaul 16216 Dez 5 2012 dynamic_master.vhd
-rw-r--r-- 1 dpaul dpaul 9126 Dez 5 2012 filter.vhd
-rw-r--r-- 1 dpaul dpaul 87884 Dez 5 2012 iic_control.vhd
-rw-r--r-- 1 dpaul dpaul 10465 Dez 5 2012 iic_pkg.vhd
-rw-r--r-- 1 dpaul dpaul 28723 Dez 5 2012 iic.vhd
-rw-r--r-- 1 dpaul dpaul 57006 Dez 5 2012 interrupt_control.vhd
drwxrwx--- 2 dpaul dpaul 4096 Apr 20 13:24 proc_common_v3_00_a
-rw-r--r-- 1 dpaul dpaul 58291 Dez 5 2012 reg_interface.vhd
-rw-r--r-- 1 dpaul dpaul 7136 Dez 5 2012 shift8.vhd
-rw-r--r-- 1 dpaul dpaul 7033 Dez 5 2012 upcnt_n.vhd
The top-module and many other design files for this IP uses the libraries axi_lite_ipif_v1_01_a, proc_common_v3_00_a, may be others. One can clearly see in the above dir structure that 'axi_lite_ipif_v1_01_a' and 'proc_common_v3_00_a' are directories and they contain many .vhd files.
So my question how do I make my Synplify TCL script aware of these libraries?
Duration simulation, I never compiled the files under dir 'axi_lite_ipif_v1_01_a' and 'proc_common_v3_00_a' directories.
THe reference manual shows something like:
add_file -vhdl -lib {work, my_lib1, my_lib2} files.vhd
But the above command dosent't help. Do I need to compile these additional libraries into 'work'? If yes, how do I do this?