[SOLVED] [Moved]: Active devices under Fringe capacitor or MOM capacitor

Hi ,
I am working in 0.13um UMC process, and I want to use a MOM cap in metal layers 3 to 6. But I am finding that LVS does not pass if I have active devices under the capacitor.
I did not find anything in the documentation saying that I cannot do so. Does anyone have experience with this?
Assuming that cross coupling is not an issue, what are the disadvantages of having active under such capacitors?
Thanks.

Re: Active devices under Fringe capacitor or MOM capacitor

Underlying topography makes the bottom plate nonuniform
(not-flat) and this can affect the dielectric's uniformity,
its local breakdown and reliability and perhaps a bit of
mismatch as well. If the foundry didn't characterize and
qualify the effects of topography-under-capacitor, they
will likely not allow it. Not just the active area but the
metallization contacting it, but anything at all can make
for nonuniformity.

Now a "MOM cap" as in simple metal-ILD-metal-ILD-...
should not care. But one with an engineered-for max-
C-density (hence, minimum dielectric thickness, as
defined by what is repeatable and reliable in production)
can be compromised.

If the "MOM cap" is indeed just an opportunistic stacking
of plain metal and ILDs, then I'd guess the problem is
simply that nobody looked at the circuit-under-cap case
and nobody wanted to sign off on the modeling being
dead-nuts regardless. Because the same metal and
dielectrics would be omnipresent and entirely allowed.

In this latter case you might have to flatten the cap once
drawn to your satisfaction and delete any recognition
layers that might key the complaining. But then you might
lose LVS. Fallback plan would be to replace the schematic
MOM instance with a pcapacitor of equal value to what the
PCell drew from.

Re: Active devices under Fringe capacitor or MOM capacitor

Hi Dick,

Thank you for response. Your feedback helped me confirm my hypothesis that for my design I can put the active devices under the cap. The issue that I was having to pass LVS was that in the dig cell that I was placing under the cap did not have a layer that the mos pcells had in them. This did not impact lvs in the regular chip area, but under the cap it did. But on adding the layer to the dig cell I was able to pass LVS.