[Moved] A problem in simulation in PlanAhead

I am new in simulation of xilinx. I created a project and added a source as embedded system and added registers as custom peripheral. I have problem in the results of simulation. I have programmed to change a value of the register but there is not any changes in simulation. Do any body know why?

The steps of creating the project is as follow:
1. Launch PlanAhead 14.2
2. Create a new project: name=>RTL sources => skip=>skip=>skip=>boards(virtex-6)=>finish
3. Add source: add or create embedded system source=>Module name: robot=>finish
4. XPS=>BSB=>PLB system=>(welcome)skip=>(board)skip=>(system)single processor=>(processor)skip=>(peripheral)skip=>(cache)skip=>finish
5. Create or import peripheral:=> skip=>(create template for a new peripheral)next=>(an XPS project)next=>name:my_custom_ip=> bus interface: PLB v 4.6=>(user logic software register & include date phase timer)checked=> (slave interface)=>number of SW accessble register=10 =>(IPIC)=>(generate BFM simulation platform)checked=>(generate ISE and XST projects files to help you … & Generate template driver files to …) checked=>finish

Changes in vhdl files:
..\project_test\project_test.srcs\sources_1\edk\robot\pcores\my_custom_ip_v1_00_a\hdl\vhdl\user_logic.vhd
6. Assign new port:
-- ADD USER PORTS BELOW THIS LINE ------------------
slv_reg0_output : out std_logic_vector(0 to 31);
--USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------
. . .
begin
slv_reg0_output <= slv_reg0;
--USER logic implementation added here
....
..\project_test\project_test.srcs\sources_1\edk\robot\pcores\my_custom_ip_v1_00_a\hdl\vhdl\my_custom_ip.vhd
7. port (
-- ADD USER PORTS BELOW THIS LINE ------------------
slv_reg0_output : out std_logic_vector (0 to 31);
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
. . .
port map (
-- MAP USER PORTS BELOW THIS LINE ------------------
slv_reg0_output => slv_reg0_output,
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE --------------

8. create or import peripheral: skip=> import existing peripheral=>(to an XPS project)=>selected (my_custom_ip)(yes)=>(HDL source files)checked=>(using existing peripheral analysis order file(.pao))checked(browse:\my_custom_ip_v1_00_a\data\my_custom_ip_v2_1_0.pao)=>next=>(PLBV 46 Slave)check=>skip=>(parameter) baseadder & highadder =>(select and configure interrupt)unchecked=>skip=>skip=>finish

9. Add ip : my_custom_ip
10. Bus interface: my_custome_ip=> SPLB=mb_plb
11. addressess: Generate Addresses
12. port: slv_reg0_output: make external
Close XPS
13. create Top HDL: robot_stub.v
14. create the TestBench: this step will create robot_top_tb.v=> replace (robot with robot_stub)
15. generate synthesis, implementation and simulation
16. File=>Export=> Export HW for SDK
17. file=>new=>c project xilinx=> hello world
18. copy “my_custom_ip.h” to \project_test.sdk\SDK\SDK_Export\hello_world_0\src
19.change the code as follow:
#include <stdio.h>
#include "platform.h"
#include "my_custom_ip.h"
void print(char *str);
int main() {
init_platform();
MY_CUSTOM_IP_mWriteSlaveReg0( 0xC8200000, 0, 0x12345678);
cleanup_platform();
return 0; }

And content of xparameters.h is shown:
...
/* Definitions for peripheral MY_CUSTOM_IP_0 */
#define XPAR_MY_CUSTOM_IP_0_BASEADDR 0xC8200000
#define XPAR_MY_CUSTOM_IP_0_HIGHADDR 0xC820FFFF
After that close SDK.
20. Run behavioral simulation
Results of simulation is attached. there is not any changes in signals, specially for signal slv_reg0. why?
thanks

Are you expecting someone to do all these steps and see if you did something wrong?

Just post an archive of the project. You might have a better chance of getting an answer. I for one am not going to try following all these steps.

I donot expect it! maybe there is someone that he has similar experience.
files of my projects are large(35Mb). if a person want them, I can send.

thanks