[Mov]generating cosine using DDS IP core when i port map to the CIC filter o/p Is XXX

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akhil.592

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I'm generating an cosine wave using DDS (sys_CLK- 200 KHZ | O/p freq - 4KHZ)IP core and i'm port mapping it to the CIC filter (clock- 125MHZ sampling - 200KHZ) the O/p of the cic filter is "XXXXXX"" please help me I've to submit my thesis
if any mistake is done please let me know


Code Verilog - [expand]
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module DDS_AUG_22(input clk,
            input clk_125m,     
    inpuk_250m                                          );
 
wire [5:0] cosine,sine;       //DDS
wire [19:0] real_part;      // CIC
wire rdy,nd;
wire [15:0] temp, din;
 
assign temp  = {cosine,10'b0000};
assign nd =  rdy; 
 
DDS ip_1(
  .clk(clk),                       // input clk
  .rdy(rdy),                    // output rdy
  .cosine(cosine),             // output [5 : 0] 
  .sine(sine)         // O/P[5:0]               
               );
 
 
COMB_FILTER Real (       
.din(cosine),           // input [15 : 0] din
.nd(nd),                   // input nd  
.clk(clk_125m),        // input clk
.dout(real_part),            // output [19 : 0] dout    .rdy(rdy_1),     // output rdy
.rfd(rfd)  );       // output rfd
 
Last edited by a moderator:

I believe both another forum member and I responded to this post, but now that it has been moved it no longer has those responses and a search didn't come up with any other similar posts for cosine DDS that matches the original post.

What is the point of moving threads if it corrupts the integrity of subsequent responses?

- - - Updated - - -

akhil.592 said:
I'm generating an cosine wave using DDS (sys_CLK- 200 KHZ | O/p freq - 4KHZ)IP core and i'm port mapping it to the CIC filter (clock- 125MHZ sampling - 200KHZ) the O/p of the cic filter is "XXXXXX""
Click to expand...
How are you handling the clock domain transfer between the 200KHz (with output at 4KHz) and the 125MHz sampling (as the DDS and the COMB_FILTER are directly connected to each other)? I suspect you have only a theoretical understanding of signal processing and don't understand that you can't just sample stuff across asynchronous clock domains in real hardware. Perform a google search on metastability for some insight on why you shouldn't.

please help me I've to submit my thesis
Click to expand...
useless information...if your submission deadline was so close maybe you should have started working on this earlier.

Bad habit using Real as the instance name as real (lowercase r) is a Verilog keyword.

As you didn't supply the code for the DDS and the COMB_FILTER it's impossible to tell why you might have X's at the output. Do you have a testbench?
 

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