MOSFET with separate gate drive channel

Hi,
The below is a 4 pin NFET.

Is the idea so that the gate drive current spike doesnt go through the source sense resistor?
...and then its possible to have small duty cycle switching without errors?
(ie the gate drive currnet pulse can't spuriously turn off the fet when a low duty (on time) is needed.)


IPZ65R045

Hi,

bonding wires are impedances...and they carry a lot of current, pulsed current...
surely causing voltage drop between die_source to source pin.

Thus an extra source pin for driving the gate without high load current will cause less voltage drop.
I expect it reduces ringing while getting increaed dV/dt.

Klaus

Thanks, but if they really have done this..ie, made an extra source terminal that somehow magically doesnt conduct the power current , but only conducts the gate drive current, then this is amazing....so why is it not more popular?....for one thing it solves the problem of low duty cycle SMPS...where a small on_time often means that the current mode ramp is obliterated by the gate drive current pulse.

I mean.....if it really does this, then for a start......things like "emulated current mode" (ECM) isnt needed any more....ECM is partly used for when a low on_time would mean the current sense ramp signal gets obliterated by the gate drive pulse

because load currents can really spike up for a 47 m-ohm fet at turn on - the extra ( kelvin connection if you like ) for the source allows precise gate drive - without the GD signal being corrupted by the load current turn on pulse - and correspondingly, also if you are applying 5A to the gate for fast turn on & turn off - then this is isolated from load current measurements too - often a good thing ...

The prerequisite of utilizing the kelvin source connection is an isolated gate driver. I feel that post #1 and #3 don't consider this simple point, e.g. when it states "an extra source terminal that somehow magically doesnt conduct the power current". But there's no magic, just an isolated gate driver. The kelvin source separates Lsource di/dt voltage drops from the gate voltage and optionally gate current from a source current sense.

4 terminal packages are very popular for SiC MOSFET due to higher switching speed and respectively lower switching losses.

Thanks, i kind of see the analogy with an isolated gate driver.
So it seems that this "auxiliary" source connection is not actually directly connected to the normal "Power" source connection of the NFET.

Regarding this meaning that the sudden power current pulse (when fet turns on) in the source_sense resistor and "power" source inductance makes the gate kind of turn more off in response to it...some would say that that is a good thing as it kind of reduces EMC problems. (makes the turn on di/dt less harsh) ...so not sure if 4 term fet is such a great advantage here?

Regarding the advantage of "no obliteration of source sense signal", again, i see the advantage, but many would say that controller LEB feature solves this anyway.

So it kind of looks to me that the main advantage of 4 term fet is in PFC, where near the mains peak, the duty cycle may get vary low, and so having a good source sense signal (due to the 4 term fet) is a great advantage......But having said that, most CCM PFCs use a ground situated sense resistor anyway...so its irrelevant for them. BCM PFCs use a source sense resistor, but they have pretty well zero turn on loss anyway as they start from zero current.

So 4 term fets seem "nice to have" but often possibly "not worth the extra cost"?

The extra source pin is more for keeping source
current out of the gate drive current loop (as
much as practical). Think of it as a local "star
ground" at the FET pads. Then you have to
think about which ground is -the- ground
and how to decouple and so on.

The source and Kelvin source are separate
pins but common inside at some point.

Usually the extra pin is only needed for high speed ( 10nS edges ) - higher current applications - because of dv/dt & di/dt - special care as to heatsinking is also required so as not to propagate RFI in the control and else where ...

Usually the extra pin is only needed for high speed ( 10nS edges ) - higher current applications - because of dv/dt & di/dt -

Click to expand...

Thanks, this is interesting, because switching on the fet quickly in a Boost PFC is usually bad because SiC diodes can't handle the high dv/dt?

SiC are better than most - careful trade-off in design needed ...

The idea is basically to reduce common source inductance (CSI) between the drive circuit and the power circuit. Making effective use of it requires careful design so that the separation of the two paths is maintained outside the FET as well.

I wouldn't say it requires an isolated gate driver, certainly not a fully isolated driver. Depends on the specific topology your working with.