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Maximum switching frequency is determined by its switching times. Switching times (e.g. delay, turn off, turn on etc) are given in a datasheet for a specific test.
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Turn ON Delay time is the time it takes the semiconductor to reach threshold voltage.
Rise time is the time it takes to the semiconductor to reach its final value measured after threshold value is reached.
Turn on time = delay + rise
Turn OFF delay time = It is the time from when Vgs drops below 90% of the gate drive voltage to when the drain current drops below 90% of the load current.
Fall time = is the time it takes the voltage to reach threshold voltage after the delay time.
Turn off time = delay + fall.
In practice, the rise and fall times of power MOSFETs are usually determined by the gate drive circuit, i.e. how fast can it charge and discharge the large MOSFET gate capacitance.
For fast rise and fall times, this can require gate drivers capable of sourcing and sinking peak currents of several amps for large MOSFETs.
Most often the chosen frequency is not limited by the
FET's own capability, but outcome tradeoffs like the
switching losses you can stand, EMI, available external
components and the BOM cost thereof. Often MOSFET
selection is done to optimize the efficiency and cost,
without regard to the ultimate cutoff frequency or the
like.
A rough corner frequency of usefulness would be
1/(Rg*Cdg) but that disregards efficiency and so on,
and gate resistance is often not a provided spec.
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