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I think your equation has a sign error, should be Ig = [(Vg-Vth)+(Vg – Vpb)] / [2 * (Rgint + Rgext)], which gives Ig = 2.30. Though for calculating t1 you'd want to do Ig = ((Vg-Vth)+(Vg)) / (2 * (Rgint + Rgext)) = 3.09A, giving t1=1.46ns.

I get 3.6ns

Math mistakes aside, you're correct that the delay times in the datasheet are far longer than what would be predicted by the simple charge+resistance model.

I think the explanation must be parasitic inductance.

As a sanity check, let's insert inductances into the model and estimate roughly what effect they would have. First lets pretend there's a gate inductance of 5nH (Lg=5nH). In the interval t2 (which lasts about 3.6ns, according to the simple model), the gate current Ig rises from zero to 2A, so dIg/dt = 0.56 A/ns. This would cause a drop of 2.8V across Ls, which is a significant fraction of the overdrive voltage (18-8=10V). So gate inductance is expected to slow us down a bit.

Let's also check how source inductance might affect things. Lets suppose there's a source inductance of just 1nH (Ls=1nH). In the interval t1 to t2 (which lasts about 2ns, according to the simple model), the drain/source current Id rises from zero to 15.7A, so dId/dt = 7.9 A/ns. This would cause a drop of 7.9V across Ls, which is nearly equal to the overdrive voltage.

The datasheet doesn't provide inductance numbers, but they probably aren't far off (probably at least half of my guesses).

Also note in the Vishay app note, they assume a very large external gate resistance of 350 ohms. This slows things down so much that parasitic inductance likely has insignificant impact (though this begs the question of why they would make such a slow circuit...).