MOSFET rise time – discrepancy between methods

[HippopotamusXD]

I’m trying to determine energy loss per switching event of a MOSFET, specifically IMT40R025M2HXTMA1 (https://hr.mouser.com/datasheet/2/196/Infineon_IMT40R025M2H_DataSheet_v02_00_EN-3483370.pdf). I’ve tried a few different methods, and none of them line up with each other or with values in the datasheet.

As per it’s datasheet table 9, td(on) is the time between applying voltage to the gate and the Vds starting to fall. The datasheet also defines tr as the time it takes for Vds to change from max to 0. Looking at diagram 16, the Vgs = f(Qgate) curve, td(on) is defined by how quickly you can bring the gate charge to 10nC, while tr is defined by how quickly you can change the gate charge from 10 to 21nC. The time it takes to change from Vth to the beginning of the plateau is defined by how quickly the gate charge can be changed from 5.5nC to 10nC.



Some common values used in all the calculations are:

Vth – 4.5V

Vpb – 8V (beginning of Miller plateau)

Rgint – 3.3Ohm

Rgext = 1.8Ohm

Td(on) – 12.5ns



My first attempt was from this video @24:10

This method approximates the gate current for the period between Vgs reaching the threshold (Vth) and the beginning Miller plateau (Vpb), and dividing the change in charge needed to do so by that current. He calls that time t1. Note that as t1 is the time it takes for Vgs to change from Vth to Vpb, it should be shorter than td(on) (time it takes to rise from 0 to Vpb)

Using values of Vg = 18V (voltage on the gate, from the driver) and Rgext = 1.8Ohm, as used in the datasheet to define td(on) and tr, I’d expect to get similar values.

Ig = [(Vg-Vth)-(Vg – Vpb)] / [2 * (Rgint + Rgext)] gives Ig = 0.343A. For the gate charge change of 4.5nC this gives t1 = 13.1ns.

This doesn’t line up with the datasheet, because for the same Rgext and Vg, td(on) is 12.5ns and td(on) should be shorter than t1.



My second attempt was from
https://www.ti.com/lit/ml/slua618a/...108019&ref_url=https%3A%2F%2Fwww.google.lt%2F



Ig2 is defined as the current during which Id changes from 0 to max on Figure 4. This should correspond to Vgs changing from Vth to Vpb. Equation 11 gives an approximation for it.

Ig2 = [Vg – 0.5(Vpb + Vth)] / (Rgint + Rgext)

Same as before, for Vpb = 8, Vth = 4.5, Rgint = 3.3 and Rgext = 1.8. This gives Ig = 2.3A, and fot Q = 4.5nC this gives t = 1.95ns. So far so good. This approximated the average current as the voltage difference between the driver voltage and the average of the voltage change we were looking for.

Expanding this not to be from Vth to Vpb, but 0V to Vpb I’d expect to get td(on).

Pllugging in 0 instead of Vth and 10nC instead of 4.5nC I get 3.64ns, which again doesn’t line up with td(on) from the datasheet (12.5ns).



Third method I tried is from
https://www.vishay.com/docs/73217/an608a.pdf



This method uses gate resistors and the input charge. On figure 2 it defines t2 as the time it takes for Vgs to reach the Miller plateau ( td(on) from the original datasheet ). Equation 12 should give that time.

t2 = Rg*Ciss*ln( 1 / (1-Vpb/Vg) )

Rg = Rgint + Rgext = 5.1Ohm

Ciss = 1.2nF

Vpb = 8V

Vg = 18V



This gives t2 = 36ns, once again not lining up with td(on) = 12.5ns from the datasheet.



This was just the part of the calculation for the time it takes for the current to switch, I’m also having trouble finding the time it takes for the voltage to switch, as all the methods assume the plateau voltage is constant but the Vgs = f(Qg) diagram shows that to not be the case for this MOSFET.

Any help or further reading resources are appreciated.

 

[mtwieg]

My first attempt was from this video @24:10

....

Using values of Vg = 18V (voltage on the gate, from the driver) and Rgext = 1.8Ohm, as used in the datasheet to define td(on) and tr, I’d expect to get similar values.

Ig = [(Vg-Vth)-(Vg – Vpb)] / [2 * (Rgint + Rgext)] gives Ig = 0.343A. For the gate charge change of 4.5nC this gives t1 = 13.1ns.

I think your equation has a sign error, should be Ig = [(Vg-Vth)+(Vg – Vpb)] / [2 * (Rgint + Rgext)], which gives Ig = 2.30. Though for calculating t1 you'd want to do Ig = ((Vg-Vth)+(Vg)) / (2 * (Rgint + Rgext)) = 3.09A, giving t1=1.46ns.

Third method I tried is from
https://www.vishay.com/docs/73217/an608a.pdf

.....

This gives t2 = 36ns, once again not lining up with td(on) = 12.5ns from the datasheet.

I get 3.6ns

Any help or further reading resources are appreciated.

Math mistakes aside, you're correct that the delay times in the datasheet are far longer than what would be predicted by the simple charge+resistance model.
I think the explanation must be parasitic inductance.

As a sanity check, let's insert inductances into the model and estimate roughly what effect they would have. First lets pretend there's a gate inductance of 5nH (Lg=5nH). In the interval t2 (which lasts about 3.6ns, according to the simple model), the gate current Ig rises from zero to 2A, so dIg/dt = 0.56 A/ns. This would cause a drop of 2.8V across Ls, which is a significant fraction of the overdrive voltage (18-8=10V). So gate inductance is expected to slow us down a bit.

Let's also check how source inductance might affect things. Lets suppose there's a source inductance of just 1nH (Ls=1nH). In the interval t1 to t2 (which lasts about 2ns, according to the simple model), the drain/source current Id rises from zero to 15.7A, so dId/dt = 7.9 A/ns. This would cause a drop of 7.9V across Ls, which is nearly equal to the overdrive voltage.

The datasheet doesn't provide inductance numbers, but they probably aren't far off (probably at least half of my guesses).

Also note in the Vishay app note, they assume a very large external gate resistance of 350 ohms. This slows things down so much that parasitic inductance likely has insignificant impact (though this begs the question of why they would make such a slow circuit...).

 

[HippopotamusXD]

I think your equation has a sign error, should be Ig = [(Vg-Vth)+(Vg – Vpb)] / [2 * (Rgint + Rgext)], which gives Ig = 2.30. Though for calculating t1 you'd want to do Ig = ((Vg-Vth)+(Vg)) / (2 * (Rgint + Rgext)) = 3.09A, giving t1=1.46ns.

I'm not exactly sure what that formula's supposed to be, I didn't find an explanation I can intuitively understand, but in the video [(Vg-Vth)-(Vg – Vpb)] is used. I didn't really understand the equation, but your version with + makes sense. It's (average voltage change)/Rg, where the average voltage hange is (voltage difference at beggining + voltage difference at end) / 2, right?

I get 3.6ns

You're right, I think I used 12nF in my calculation instead of 1.2nF

Using Ig = ((Vg-Vgp)+(Vg)) / (2 * (Rgint + Rgext)) also gives the figure around 3.6ns so I'll assume both of those methods are good for me for now.

Math mistakes aside, you're correct that the delay times in the datasheet are far longer than what would be predicted by the simple charge+resistance model.
I think the explanation must be parasitic inductance.

As a sanity check, let's insert inductances into the model and estimate roughly what effect they would have. First lets pretend there's a gate inductance of 5nH (Lg=5nH). In the interval t2 (which lasts about 3.6ns, according to the simple model), the gate current Ig rises from zero to 2A, so dIg/dt = 0.56 A/ns. This would cause a drop of 2.8V across Ls, which is a significant fraction of the overdrive voltage (18-8=10V). So gate inductance is expected to slow us down a bit.

Let's also check how source inductance might affect things. Lets suppose there's a source inductance of just 1nH (Ls=1nH). In the interval t1 to t2 (which lasts about 2ns, according to the simple model), the drain/source current Id rises from zero to 15.7A, so dId/dt = 7.9 A/ns. This would cause a drop of 7.9V across Ls, which is nearly equal to the overdrive voltage.

That looks very iterative to me, like you'd get t1 with just Vg, plug in that t1 to get voltage drop on the inductance, return to calculating t1 with (Vg - V_Ls - V_Lg), that would give you a more accurate voltage drop on the inductance so you'd return to calculating t1... Do you maybe know of a method that immediately takes the inductance into consideration?

Also note in the Vishay app note, they assume a very large external gate resistance of 350 ohms. This slows things down so much that parasitic inductance likely has insignificant impact (though this begs the question of why they would make such a slow circuit...).

I noticed that, it was very strange to me that they had such variation in the calculated and measured times.

 

[dick_freebird]

Might look into gate drive network differences
including things that aren't said - like a lazy app
figure recapture might omit that one is a 50-ohm
ATE source and another is a MOSFET driver on
the load board, or one direct drives while another
has gate up / down resistors. Fat gate means all
that kind of thing matters. And maybe after you're
all done all you have is a (N+1)th disagreement.
Heh.

 

[mtwieg]

I'm not exactly sure what that formula's supposed to be

I believe [(Vg-Vth)+(Vg – Vpb)] is supposed to be the average voltage across Rg+Rext during the interval between t1 and t2.

That looks very iterative to me, like you'd get t1 with just Vg, plug in that t1 to get voltage drop on the inductance, return to calculating t1 with (Vg - V_Ls - V_Lg), that would give you a more accurate voltage drop on the inductance so you'd return to calculating t1...

I wasn't suggesting an actual method of calculating these times with inductance. Just showing how the inclusion of inductance can make the simpler model's predictions unreasonable.

Do you maybe know of a method that immediately takes the inductance into consideration?

No, and I doubt there is a straightforward analytical solution. This is where I would turn to SPICE simulation. Also in practice, the parasitic inductances usually need to have some damping applied (usually in the form of some parallel resistance) in order to behave realistically.

If you look at Infineon's product page, they offer SPICE models which seem to include these parasitics. I would start there.

 

[cupoftea]

As well as stray inductance to make a mess of switching loss calcs, theres sometimes the reverse recovery of whichever diodes, which send a huge spike of current through a fet when it turns on.....eg in a boost converter PFC.

I like the equns in Laszlo Baloghs doc as follows, for sw losses...but they dont come out too accurate....at least they dont agree with eg ti.com sw loss calculator

http://www.radio-sensors.se/download/gate-driver2.pdf#:~:text=By%20Laszlo%20Balogh.%20ABSTRACT.%20The%20main%20purpose%20of%20this%20paper