MOSFET parasitic capacitance and charge

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Bjtpower_magic

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Hi,

I have started working on Mosfet analysis, i have to replace IRFZ44VPbF (https://www.infineon.com/dgdl/irfz44vpbf.pdf?fileId=5546d462533600a40153563b51fa2214) with alternate mosfet which is IRF60B217 (https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d46256fb43b301576e3c7f77665e)

i have done pre analysis of both the Mosfet and have found below parameters.
Column 2 is for IRFZ44VPbF and Column 3 for IRF60B217
Typical Gate to Drain Charge (nC)2514
Typical Input Capacitance @ Vds (pF)1812@25V2230@25V
Typical Turn-On Delay Time (ns)138.3
Typical Turn-Off Delay Time (ns)4024
Typical Fall Time (ns)5720
Typical Rise Time (ns)9737

I tried to read Mosfet capacitance effect and gate to drain charge but i did not find any relation well explained and confused after reading lot of datasheet.

Can you please help relationship with other important parameters, some equations?
I have Flyback converter (Already designed by ex colleague, who left organization )
Input: 20-32VDC
Ouput: 5V at 8A
Switching Frequency: 100 khz
Gate driver : UCC3809 https://www.ti.com/lit/ds/symlink/u...ttps%3A%2F%2Fwww.ti.com%2Fproduct%2FUCC3809-2
 

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Easy peasy said:
a ~ 70nS turn on plateau is fairly accpetable, what does the turn off look like ? what gate R's are you using ?
Click to expand...
Captured with more accurate oscilloscope
Offtime

Ontime:

--- Updated ---

Easy peasy said:
" How do you know 70nS is acceptable? "

. . . have designed about 70 power supplies to manufacture and sale.
Click to expand...
Hi,
I mean is there any criteria from Datasheet of Thumb rule for Plateau time? What is acceptable range? how to derive it? Sorry for asking too much questions but honestly i am trying to understand.
 

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Bjtpower_magic said:
I mean is there any criteria from Datasheet of Thumb rule for Plateau time?
Click to expand...
For sure the plateau depends on:
* drive current
* MOSFET capacitance
* switching voltage
* and so on
...

But you may adjust it on your needs:
* some go the "slow" way to keep noise (ringing, EMI) low
* I prefer the faster way, but it needs a more "low inductive" PCB layout, to keep EMI low. Faster switching usually also means less switching loss.

So if you are not very experienced with high frequency switching PCB layouts, you rather go with longer switching times to prevent from ringing / EMI problems.

Klaus
 
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Every design has to balance conduction and switching losses in optimizing
gate drive. Miller plateau time @ current is a conduction loss which
masquerades as a switching loss (as for a fixed drive, load and VIN the
plateau delivers a "loss slug" every cycle, so frequency dependent).

If driver and FET Cgs dominates switching losses then soft switching is
a play. But that leaves the inductor current to pull the high side FET
source and low side drain, down (at least this is circulating, not shunt
loss current). It has nothing for the L-H transition anyhow. Hard
switching IME delivers the best efficiency (as well as coast-to-coast radio
coverage).
 
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really - the gate rive is determined by the Vds dv/dt at turn on / off, and to a lesser extent the di/dt at turn on,

this is because a product needs to pass EMC standards, and turning on too hard, and off too hard can cause RF noise if the layout is not optimum.
 
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Hi All,
Thanks for your responses.

I hope this post will help everyone who would like to understand Mosfet and Gate drives, it has helped me a lot.
Thanks once again all of you to have a great discussion, Keep discussing.. Keep helping.
 

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Hi,
Is there any relation of Load vs gate drive voltage.
I have observed that Vgate_Plateu voltage changes with load.

Gate drive with 10% load


Gate drive with 50% load:
 

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Bjtpower_magic said:
Is there any relation of Load vs gate drive voltage.
Click to expand...
With load .. you mean "load current"?
What are you expect it to express?

I mean, for sure V_GS controls the conductivity of a MOSFET, thus it surely has influence on I_D.

****
Bjtpower_magic said:
I have observed that Vgate_Plateu voltage changes with load.
Click to expand...
Again: you mean "load current"?
The timing of the plateau depends more on switching voltage than on switching current. But for sure there is some kind of influence.
And the "load current" , or better say the I_D has influence on the level of the plateau. Especially on MOSFETs with low g_m.

Klaus
 
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Yes.. Output Load.
Secondary of Flyback.
1. Loaded with 10% of full load.
2. Leaded with 50% of full load.
--- Updated ---

mtwieg said:
The fall in Vgs during turn-on at light load is odd. Capturing the Vds waveform at the same time would probably show the reason why...
Click to expand...
VGS at 1A


VDS at 1A
 
Last edited:

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Hi,
Bjtpower_magic said:
Yes.. Output Load.
Click to expand...
I was not clear in this. I expected to differ between load_voltage and load_current.

But indeed, when we talk about a MOSFET, then lets use the MOSFET terminology, like: V_GS, I_D, and so on,

******
The fall in Vgs during turn-on at light load is odd
Click to expand...
I agree.
* measurement artefact?
* stray inductance?
* capacitive coupling?

The scope pictures of post#50 don´t have the same timing reference, but we need this for a good analysis.
I guess your scope has more than 1 channel, so please show both channels in one scope picture.

Klaus
 

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