MOSFET parasitic capacitance and charge

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Bjtpower_magic

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Hi,

I have started working on Mosfet analysis, i have to replace IRFZ44VPbF (https://www.infineon.com/dgdl/irfz44vpbf.pdf?fileId=5546d462533600a40153563b51fa2214) with alternate mosfet which is IRF60B217 (https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d46256fb43b301576e3c7f77665e)

i have done pre analysis of both the Mosfet and have found below parameters.
Column 2 is for IRFZ44VPbF and Column 3 for IRF60B217
Typical Gate to Drain Charge (nC)2514
Typical Input Capacitance @ Vds (pF)1812@25V2230@25V
Typical Turn-On Delay Time (ns)138.3
Typical Turn-Off Delay Time (ns)4024
Typical Fall Time (ns)5720
Typical Rise Time (ns)9737

I tried to read Mosfet capacitance effect and gate to drain charge but i did not find any relation well explained and confused after reading lot of datasheet.

Can you please help relationship with other important parameters, some equations?
I have Flyback converter (Already designed by ex colleague, who left organization )
Input: 20-32VDC
Ouput: 5V at 8A
Switching Frequency: 100 khz
Gate driver : UCC3809 https://www.ti.com/lit/ds/symlink/u...ttps%3A%2F%2Fwww.ti.com%2Fproduct%2FUCC3809-2
 

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Hi,
Which tr and tf are you cosnidering.
Gate driver has different values and Mosfet has different values.
Which needs to consider?

Also you only considered Qgd and not Qgs which is also important, What do you think?
My Switching frequency is 135KHZ, Total cycle time=7.4uS, Max Turn on Time: 3.7uS?
does it help for pre analysis for gate current ?
--- Updated ---




--- Updated ---

 

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Bjtpower_magic said:
Which tr and tf are you cosnidering.
Gate driver has different values and Mosfet has different values.
Which needs to consider?
Click to expand...
What you do with those equations is up to you. There's (at least) two options:
1. If your gate driver can provide some currents Isource and Isink, and your FET has some Qgd. Therefore the switching times will be roughly tr=Qgd/Isource and tf=Qgd/Isink
2. If you want specific switching times tr and tf, and your FET has some Qgd. Therefore your driver must provide currents Isource=Qgd/tr and Isink=Qgd/tf
Bjtpower_magic said:
Also you only considered Qgd and not Qgs which is also important, What do you think?
Click to expand...
To a first order, Qgs does not affect rise and fall times on the drain. It does affect rise/fall/delay times on the gate though.
 
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Hi,

rather good informations here.

But IF you want to get a deeper understanding in how to drive MOSFETs I recommend to read some Design notes and Appliaction notes. Almost every MOSFET or MOSFET_Driver manufacturer provides them.


****

The problem is rather complex. Wiring, PCB layout, GND plane, bypass capacitors .. everything plays a role.
I don't want to confuse you with details, so - in case - you may stop reading here ;-)

In post #1 you wrote:
IRFZ44VPbFIRF60B217
Typical Fall Time (ns)5720
So it seems the rise rate of the IRF60 is 3 times faster. But this is not true, because the values are obtained under different conditions:
IRFZ44VPbFIRF60B217
V_gate_drive (V)1010
V_GS (V)5.5V (chart)5.0V (chart)
total drive impedance (Ohms)9.12.7
VDD(V)3030
I_D (A)5136
Fortunately the voltage thresholds for the timing measurements are identical (10%, 90%) for both MOSFETs.

If we take these values into account then the gate current is about:
I_G = (V_gate_drive - V_GS) / impedance.
Then we get about: 0.49 A for the IRFZ44 and 1.85A for the IRF60.

You see this are really different gate drive conditions.

But wait,now I´m worried: If this is true, then when you drive the IRF60... with the same current than the IRFZ44 then the fall time is considered to be 75.5ns. This means it is slower than the IRFZ44. There must be a mistake!
So we verify the numbers according gate charge:

IRFZ44:
Miller charge (Q_GD during t_f) = 25nC; according Fig6: 35nC - 13nC = 22nC --> let´say both values match
C_oss = 393nF
fall time t_f = 57ns
Gate current = Q/t = 25nC/57nF = 0.43A ... let´s assume this is O.K.

IRF60:
Miller charge (Q_GD during t_f) = 14nC; according Fig8: 26nC - 12nC = 14nC --> perfect match
C_oss = 230nF (energy related)
fall time t_f = 20ns
Gate current = Q/t = 14nC/20nF = 0.7A ... this sounds more plausible.
(it´s a factor of about 4 off!)

So my conclusion:
* maybe I did get something wrong ...
* or there is an error (or some information missing) in the datasheet. For me the 2.7 Ohms is a bit low as total drive impedance. Maybe the digits are swapped: 7.2 Ohms makes more sense.

--> I guess there is in issue with the gate drive informations in the datasheet.

Klaus
 
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What is a factor of 4 off?
KlausST said:
* maybe I did get something wrong ...
Click to expand...
I don't think you made any mistakes, but I don't think this analysis is giving the OP the answer they want (my point is there is no magic equation for designing this stuff, unless the designer specifies something else first).
KlausST said:
* or there is an error (or some information missing) in the datasheet. For me the 2.7 Ohms is a bit low as total drive impedance. Maybe the digits are swapped: 7.2 Ohms makes more sense.
Click to expand...
Yes thanks for pointing out the big difference in the gate resistance used for the tr/tf measurement, that is peculiar. It's likely that if the FETs were measured in the same test fixture the tr/tf values would be much closer. Just goes to show how arbitrary some of these specs are...
 
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Hi Klaus,

Thanks for detail explanation.
Now its pretty clear and good informative for others as well.

I have last doubts.
I see you considered Fall time and not Rise time
Rise time for IRZ44=97nS
Rise time for IRZ44=37nS

I have rearranged equations:
IRFZ44:
Miller charge (Q_GD during t_f) = 25nC; according Fig6: 35nC - 13nC = 22nC --> let´say both values match
C_oss = 393nF
fall time t_r = 97ns
Gate current = Q/t = 25nC/97nS =0.25A 0.43A ... let´s assume this is O.K.

IRF60:
Miller charge (Q_GD during t_f) = 14nC; according Fig8: 26nC - 12nC = 14nC --> perfect match
C_oss = 230nF (energy related)
fall time t_r = 37ns
Gate current = Q/t = 14nC/37nS =0.37A 0.7A ... this sounds more plausible.
 

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Hi,

Well done.
Q is about the same for falling and rising
Thus current is proportional to 1/t.
Different is, that now the current inside the gate driver goes to GND.
Thus for resistance you need to use V_GS instead of (10V - V_GS)

Klaus
 

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I have never seen such " overthunkness " for a mosfet replacement . . . . in regards to gate drive

If the Cgs was way higher, or the Cdg for that matter - then you might have issues - slightly higher sw losses

but really . . . .
 

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Agreed, this is one case where someone needs to put down the calculator and pick up a soldering iron... or at least run some SPICE simulations...
 

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Hi,

As a professional electronics engineer I have to say, I always appreciate a person who wants to understand (learn) things instead of just trial-and-error without using brain.

OP says:
Can you please help relationship with other important parameters, some equations?
Click to expand...
...
I would like to Understand/Learn the relation of other parameters like gate charge, Capacitance? How it will impact on design? Any co relation of this parameters?
Click to expand...

I think that's what distinguishes a homo sapiens from all other mammals.

Klaus
 
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The gate drive current you need relates directly to the transition time
you demand (crudely, Qgg/Ipeak) and that, to details of DC-DC
operation. Like if you are after soft switching you want less, not
more, gate drive (or hold off that drive for a while, which is a bit
more elaborate done right). But extending the switch transition
time does add more switching losses within the FET itself, all the
while that the drain is not resting at either rail with either Vds or Id
at zero. Stretch the time, stretch the Joules.
 

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Hi,
Now i have done some practical experiment and have some results.
We have UCC3809 and Mosfet IRFZ44.
VDD for UCC3809:10.6V
Drain Voltage or Input Voltage: 24V
Frequency: 130KHZ
Condition: No Load.


I cannot understand this is right behavior? This waveform captured across Gate to Source (Across Mosfet Pin).
What to verify in this?
--- Updated ---

Series resistor between UCC3809 to Mosfet gate is 4.7 OHM
 

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That's the usual Miller plateau, where drain dV/dt times Cdg will
and must return a current equal to your gate drive current @
Vcc-Vplateau. There it will sit until the drain has fully swung,
then continue to charge the rest of Cgs, Cgb.
 

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dick_freebird said:
There it will sit until the drain has fully swung,
then continue to charge the rest of Cgs, Cgb.
Click to expand...
Hi,
I think it has already charged Cgs, during miller plateu where Gate voltage and Drain voltage about to equal or less than Gate voltage then Cgd comes into play and during that time, it charge Cgd.

I wonder is this behavior acceptable as shown in Scope image? How one can be sure is it fine to go ahead?
--- Updated ---

 
Last edited:

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Bjtpower_magic said:
wonder is this behavior acceptable as shown in Scope image?
Click to expand...
Looks normal to me.

The gate voltage initially rises due to the gate drive current charging the normal gate capacitance until the drain starts to turn on at T1 to T2
This causes added gate charge from the Miller capacitance, which stops the gate voltage increase due to the finite gate drive current.
When the drain has finished changing state at T3, the normal gate capacitance continues to be charged until the full gate voltage is reached at T4.
So the MOSFET source fall-time is approximately from T2 to T3.

Make sense?
 
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Hi,
Do we need to relate this with Mosfet Dataseet? How one will know that everything is well? Mosfet is turning right?
Lets say if i reduced/increased gate resistance? still i will see similar graph of VGS?
 

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