Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The positive RDS tempco helps at steady state, but keep in mind that often in order for the tempco to be positive you have to drive the gate with some minimum voltage. Check that voltage on your datasheet.
You'll have to watch out during the switching transient though, often the effect of temperature on switching times is not so simple. Preferably you'll want them to all switch equally. Having the cooler devices switch faster should be okay as well too. Worst case is hot devices switch first.
I have only one dielectric plate on that , through which the current is to be passed , to be used in an experiment and the resultant voltage drop has to be measured.
For short term DC (and impulses) the wiring layout and resistance to each fet drain and away from the source can influence the power dissipated in the devices - so try and make all the wiring paths similar and of the same DC resistance - otherwise some fets may try to pass more current than others and fail - also good heatsinking is pretty critical - try not to short out your wiring arrangements by bolting the fet tabs to each other via a heatsink (unless this is part of your design) beware the fact that heatsink paste at low volts can be a pretty good or partial insulator (if you are using the drain tab to heatsing as an electrical conducting path) - Regards, Orson Cart.
You may also want to have a derating factor applied while calculating number of FET or individual FET current rating. This would further improve the reliability.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
