Mosfet Driver Tapering Factor

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AMSA84

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Hi guys,

Can some tell me what is the tapering factor from a driver? I read in a book but I didn't understood. I know that there is a variable n = number of stages and f which I didn't understood yet what means. I am confused about this.

Regards.
 

To get current gain each stage is larger than its predecessor.
How much, is your "taper factor".

Best delay in long chains comes at about 3:1. But ultimate
bandwidth wants a lesser factor (2:1) while area comes out
better with a higher taper factor. Probably this all appears
in the paper.

Now, a power MOSFET driver is a big driver and you want
more than a simple inverter chain. The shoot-through
currents will be really bad unless you design the high side
and low side switches to have some nonoverlap, and each
of their predrivers too most likely. So you will probably end
up well off the beaten path, as far as these logic-
optimization-oriented papers' advice, before you're done.
 

Hi thanks for the quick reply.

I think for both, PMOS and NMOS power devices?

So the taper factor is the number which we multiply by to the predecessor stage? For example: 1st stage has a Wp=3 and Wn=1; the 2nd stage will be, supposing a taper factor of 3, Wp=9 and Wn=3? Then the 3rd will be Wp=9um x 3 and Wn=3um x 3...!

freebird, I didn't understood this: "So you will probably end up well off the beaten path, as far as these logic-optimization-oriented papers' advice, before you're done."

From what I've read so far is that if the last driver is large, the number of inverters in the chain will be less when compared to the situation where we have the last stage less larger. If we have less stages we'll have more speed.
 

By the way, I forgot to ask another thing.

I read in a paper that one should make the first stage as small as possible. The doubt I've here is do we need to make the inverter driver type make the transition at VDD/2? In this case I've a 3.3V power supply, which means a transition about 1.65V. The smallest transistors sizes that I can get to do this transition at VDD/2 is not so small as it should, that is, the widths are about for wn=4um and wp=15um for a transition at 1.63V, or wn=8um and wp=25um for a transition at 1.59V and for wn=6um and wp=20um for a transition at 1.60V. My doubts are:

1 - Do I need to make the transition at ~1.65V?
2 - Which one to choose taking into account that all of them have different ratio between then, ranging from 3.75 to 3.125. I read that to have a good match between the transistor they must have a ratio between 2 to 3.
4 - Should I ignore the transition at VDD/s and choose the minimum width as possible taking into account the ratio of 2 to 3? For example: wn=1um and wp=3um (transistion at 1.27 V) or wn=2um and wp=6um (transition at 1.48V)?

If I estimate rougly the input capacitance of the first stage (with the minimal sizes as possible) and estimate the input capacitance of the power device I can use the approach describe in some papers where they use those parameters to determine the tape factor and the number of inverters. Right?

Regards
 
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1 - Not necessarily, but it should lie in the middle third of the supply voltage.
2 - Depends on your process: the right factor is the ratio of the n and p low field mobilities µ0,n/µ0,p. This ratio was about 2 for >1µm processes, is ≈3 for most sub-µm processes, but I've also seen a ratio close to 5 :
4 - minimum width, yes, for the 1st stage, considering your process' mobility ratio.

Right!
 

Hi erikl,

I am working on a UMC 0.13um process. Where can I can confirm/find those low field mobilities? By the way, why are you callin low filed mobility instead of electron or hole mobility? Are the same? I thought that the electron and hole mobilities where the same in all technologies.

When you say "middle third" is > (1/3)VDD?

erikl, minimum width but considering the middle third?

By the way, to estimate the input capacitance of an inverter I can simply rougly say that the Cin = (Wn+Wp) x L x Cox?
 
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In MOSFETs at low gate field, your conduction abuts the
gate ox and you are seeing surface mobility, not bulk. The
scattering from interface traps / states degrades u0 from
the natural bulk uN, uP. Only when the channel gets
significantly deep will this improve, and the majority of
conduction always is at the surface (unless you have
constructed a "buried channel" device, and this is always
inferior net conduction due to the Vgs "lost" in uncovering
it - buried channel is done for noise, not drive).

Your input capacitance is the gate plate capacitance
plus the Miller capacitance. This latter depends effectively
on the drain voltage swing as well as cgdo. The former
varies across the input swing (C-V characteristics of the
two FETs, accumulation-depletion-inversion, superposition).
If it were me I'd just run a quickie simulation and scale
from that; analytical figuring is too messy and incomplete
to be worth much, not to mention taking longer.
 

Hi freebird,

Thanks for the advice. In fact I though in that too and I did some experiments through simulation. However I don't know if I am doing right, that is, I have selected a wn and wp for 1st the pmos driver chain and other wn and wp for the 1st nmos driver chain taking into account the un/up aprox. 3.

I selected for example, for the PMOS driver chain wn=1um and wp=3.2um. Then I thought to choose a tapering factor of 3. After that I went all the way multiplying the next MOSFET w's by 3 until I had a nice W in the last driver.

But after that I was wondering when I should stop, in a sense of for example the last stage is ~260um. If I multiply again by 3 I will have a W of 780um. Should I do this or leave it with 260um?

This was the reason to try this approach that I am discussing here; in fact I agree that it is messy and doesn't know if I would get a reasonable result.
 
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AMSA84 said:
Where can I can confirm/find those low field mobilities?
Click to expand...
In your NMOS/PMOS models. Named U0. But better use an experimental ratio (s. below), because the real mobilities may be quite different from the low field values, s. dick_freebird's comment above.

AMSA84 said:
By the way, why are you callin low filed mobility instead of electron or hole mobility? Are the same?
Click to expand...
"low field" means bulk mobility unaffected by interface, saturation and vertical field mobility reduction (VFMR) effects. Both valid for electrons and holes, each.

AMSA84 said:
I thought that the electron and hole mobilities where the same in all technologies.
Click to expand...
Never.

AMSA84 said:
When you say "middle third" is > (1/3)VDD?
Click to expand...
(1/3)VDD ≦ Vtransition ≦ (2/3)VDD

AMSA84 said:
erikl, minimum width but considering the middle third?
Click to expand...
Yes. To find the right Wp/Wn ratio, I'd suggest to run a parametric transient analysis. Vtransition=VDD/2 shows you the optimum ratio. Then keep this ratio for the following inverters.

AMSA84 said:
... to estimate the input capacitance of an inverter I can simply rougly say that the Cin = (Wn+Wp) x L x Cox?
Click to expand...
Miller cap is to be added, see dick_freebird's remark above.
 

Okay erikl. Thanks. Allow me to inform you that the Wp and Wn where the transition at VDD/2 occurs are:

1st - wn = 4um and wp = 15um -> I get a transition voltage around 1.63V. However the ratio between them are not within 2 or 3 - 3.75 (but has you said there are ratio of > 4, so that might not be such a problem).

2nd - wn = 6 and wp = 20um -> transition around 1.6V and a ratio between transistor's of 3.33;

That said, I would go for the 1st one, but I don't know if there is any problem with the ratio between them and the fact that those transistor sizes are not the minimum achievable with the technology. (for example wn = 1um and wp = 3um - although not corresponding to the best transition voltage).

I have checked the u0 in the models: for the pmos the u0 is 9.2157e-3 and for the nmos u0 is 3.04e-2. This corresponds to a ratio of 3.29871 ~3.3.
 

Hi guys, I forgot to ask one think. Should we multiply the L by the same factor that we are multiplying the W?
 


In your case, I suggest to use (and keep) a Wp/Wn ratio of 3.5

AMSA84 said:
Should we multiply the L by the same factor that we are multiplying the W?
Click to expand...
Of course not. You want to increase the W/L ratios from one buffer to the following!
 

Hi erikl, thanks for the tip. I read that one should keep the L with the minimum value and that the PMOS and NMOS should have the same L. In my case the value is 0.34um.

Regarding the ratio, I will try 3.5.

One more thing:

Supposing that I've chosen a taper factor of 2.5 and that in the first stage I am using in the first inverter, for the PMOS POWER DEVICE a Wp=3um and Wn=1um, I am suppose to scale from the first stage multiplying the previews stage by 2.5 or by 2.5 for the second by 5, the third by 7.5 and so on?

For example:

1st inverter: PMOS - 3/0.34; NMOS - 1/0.34;
2nd inverter: PMOS - (2.5 x 3)/0.34 = 7.5/0.34;
3rd inverter: PMOS - (2.5 x 7.5)/0.34 = 22.5/0.34;
or
PMOS - ((2.5+2.5)*3)/0.34 = 15/0.34
or
PMOS - ((2.5+2.5)*7.5)/0.34 = 37.5/0.32

?
 

AMSA84 said:
1st inverter: PMOS - 3/0.34; NMOS - 1/0.34;
2nd inverter: PMOS - (2.5 x 3)/0.34 = 7.5/0.34;
3rd inverter: PMOS - (2.5 x 7.5)/0.34 = 22.5/0.34;
Click to expand...
Right!

AMSA84 said:
or
PMOS - ((2.5+2.5)*3)/0.34 = 15/0.34
or
PMOS - ((2.5+2.5)*7.5)/0.34 = 37.5/0.32
?
Click to expand...
No. You have to multiply only, not add additionally.
 

Hi guys,

I am trying to make a non overlapping circuit. However I came up with a doubt while seaching some circuits.

I'll use this one: https://www.google.pt/imgres?imgurl...p_fhodWsXM&ei=4I60U-qtCYTK0QXa6oCACA&tbm=isch

1st, this particular circuit has any specific name? For example, latch based non overlapping circuit?

Regarding the circuit that I'll, what are the differences to this one: https://www.google.pt/imgres?imgurl...ct=rc&uact=3&dur=1496&page=2&start=13&ndsp=22 ???

(forget the inverters)

Now, if we consider the inverter, to the circuit that I'll be using and taking into account that is to drive power mosfets, the configuration should be something like this:

https://www.google.pt/imgres?imgurl...iact=rc&uact=3&dur=397&page=1&start=0&ndsp=13 ???

The first 2 inverters are used to introduce some delay, and the third one and furthers (not represented) are the power devices drivers, right? That will need to obay to that tappering factor?

Please, feel free to correct me and to add more info/explanations.

Hope made myself clear.

Regarads.

EDIT: I forgot to put another picture:

What are the diferences with this circuit to the others above?
 
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Hi guys, getting back this topic, I want to ask one thing.

Doing all that stuffs to get the tapering factor, imagine that we get the value 3. Now, if we want to drive a power device with a W=3000um, I want to ask:

To compute the transistors sizes we can do something like:

1st: W(of power device) = 3000um / 3 = 1000um or, we assume a bigger taper factor from the power device to the last driver in the driver chain of inverter? That is, for example, 3000um / 10 = 300um, and now we apply the tapering factor to the last driver in the chain?

2nd: Supposing that now that we have computed the size of the last driver (doesn't matter to which one of the above was applied), my question is:

I should now do: For example, 3000um / 10 = 300um - 300um is the size of the PMOS of the last driver, now I divide by 3 (due to electron mobility) and get 100um, becaming the last driver with sizes of 300um/100um?

OR

3000um / 10 = 300um is the total area of the inverter and now I have to distribute to each of the components, and for that I do 3/4 for the PMOS and 1/4 (due to the electron mobility) to the NMOS, becoming the sizes something like: 225um/75um?

After that, to compute the driver before the last one, I should grab the value of 300um (the total area for the inverter or the value it self of the PMOS of the last drivers) and divide by 3 (the tap factor) or I should divide by 3 the 225um?

Kind regards and sory for the confusing explanation
 

Taper factor = 3 is folk wisdom from inverter chain delay
optimization. If minimum prop delay is the concern, then
fine. But in a power MOSFET driver, it isn't close to the
main concern. With an output stage capable of >1A you
are much more interested in controlling the shoot-through
current (my first power MOSFET driver spit little bits of
silicon at me between the probe station microscope
eyepieces, launching ballast resistors out of their little
DI tubs).

Many users of power MOSFETs place series gate resistors
and deliberately slow the edge rate anyway; so you may be
fine with a higher taper factor at the output pair. An output
rise/fall time spec, unloaded, if any, would make the call on
gate predrive.

Inverter chains presumably would be drive-strength-balanced
device sizing, P vs N, and the 3:1 taper will be assuming this.
At least this seems to be the norm for standard cell libraries.

But again your MOSFET driver might have quite different
desired peak current values, high vs low side - an NMOSFET
specific driver for totem pole apps would want stronger, or
at least faster, low drive so that break-before-make in an
all-N totem pole happens naturally (turnoff < turnon) at the
next level of assembly.
 

But that resistor is to be place at the POWER device itself, I mean at the gate of the POWER device? What about the inverter chain? There is any way to prevent the shoot through?

Now, I am trying to arrange an alternative driver to the inverters. I was exploring all the possibilities.

- - - Updated - - -

Or you are referring to insert a resistor in series with each drain of the inverter?
 

I'm saying that since the external resistors set the real gate
risetime, and well slower than any sensible bare driver, you
need not worry about giving your final stage really stiff gate
drive - you can undersize (somewhat) the predriver devices
with no application downside and maybe some operating power
reduction.

I'm not recommending putting resistors inside the chip, that
just makes more thermal problems for you and less choices
for the end user.
 

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