[SOLVED] MOSFET datasheet not lining up with SPICE simulation

Hi,

at first I have to say: better trust the datasheet than any simulation.

But:
to compare test results you need to use the identical test setup.

* You used shorted Drain with Source
* But datasheet says: 200V and 15.7A and test setup according JEP192.
--> This is not the same at all.

I don´t know the test setup used by JEP192 ... (if you want to compare .. it´s your job to get the according informations)

Klaus

KlausST said:

* You used shorted Drain with Source
* But datasheet says: 200V and 15.7A and test setup according JEP192.
--> This is not the same at all.

Click to expand...

I ran a simulation with V_DD = 200V and a 12 Ohm resistor in series to simulate the I_D = 16A and got the same graph, only difference being that the plateau voltage is 0.3V higher (as expected because of higher V_DD) and last a bit longer (as expected because of higher I_D)



Also ran a sweep on the gate resistor value, from 1 to 10 Ohm, and got plateau voltage of around 8V for 10 Ohm, but the datasheet setup used 1.8 Ohm


I know I should trust the datasheet values more, but I'm trying to calculate switch on losses, and a lot of resources I found stated that simulations are more accurate because of the nonlinear capacitances in the mosfet, making analytical solutions inaccurate, so as a first step i wanted to verify the simple things in simulations first and got caught up on this.

Hi,

HippopotamusXD said:

I ran a simulation with V_DD = 200V and a 12 Ohm resistor in series to simulate the I_D = 16A

Click to expand...

I can´t find any information in the datasheet that they used a 12 Ohms resistor.
All I can see they used 15.7 A ... and I guess they did it this way.
It´s not the same!

Again: please look up JEP192!

Example:
While increasing V_GS ... R_DS decreases.
* With a 12Ohms resistor as load: V_DS = 200V * R_DS / (R_DS + 12 Ohms)
* With a 15.7A crrent source: V_DS = 15.7A * R_DS (limited by 200V)
--> V_DS follows different rules ... and due to the miller capacitance V_DS will influence V_GS behaviour. So it´s quite expectable to get different results.

Klaus

A difference could be the Vgs(th) in the sim model may be different than the value used in the data sheet plot.
Can you look at the sim model and see its value, or do a sim to determine Vgs(th) (curve in Diagram 11)?

KlausST said:

Again: please look up JEP192!

Click to expand...

I've looked up JEP192. It did explain why the Miller plateau isn't a horisontal line for SiC MOSFET-s and that there is a hysteresis for the threshold voltage at turn-on and turn-off, but not much about the voltage level for the start of the plateau. JEP192 boils down to using a double pulse test to determine the gate charge values. Simulating the double pulse test is what I started with and then I noticed that the plateau value doesn't line up with the datasheet.



This was the original simulation I tried, with following results


As seen by the green line, the plateau voltage is around 15V again.

HI,

you need to show a chart with V_GS AND V_DS.
The V_GS plateau is wher V_DS transitions.

It´s also a good idea to additionally show I_D, so we can see at which I_D is which V_GS.

Klaus

crutschow said:

A difference could be the Vgs(th) in the sim model may be different than the value used in the data sheet plot.
Can you look at the sim model and see its value, or do a sim to determine Vgs(th) (curve in Diagram 11)?

Click to expand...

From my limited SPICE model knowledge I found this
The model starts with

.SUBCKT S_400_sic_var dd g s0 Tj PARAMS: a=1 dVth=0 dR=0 dgfs=0 Inn=1
+Unn=1 Rmax=1 gmin=1 Rs=1 Rp=1 dC=0 Rm=1u

.PARAM Vth0=6.7 c=660m k=660m Fm=300m Fn=450m al=300m
.PARAM Vmin=6.4 Vmax=8.8 dCmax=330m
.PARAM Vth={Vth0+(Vmax-Vth0)*limit(dVth,0,1)-(Vmin-Vth0)*limit(dVth,-1,0)}
.PARAM q0={b0*a}
.PARAM q1={(Unn-Inn*Rs-Vth0)*q0}
.PARAM q2={(Fm*SQRT(0.4)-c)*Inn*q0}


...

.ENDS



And later in the model there is:



.SUBCKT IMT40R025M2H_L1 drain gate source ss PARAMS: dVth=0 dRdson=0 dgfs=0 dC=0 Ls=1.5n Ld=100p Lg=3n

.PARAM Rs=563u Rg=3.3 Rd=20u Rm=169u
.PARAM Inn=15.7 Unn=18 Rmax=32.1m gmin=5.7
.PARAM act=4.03

X1 d1 g s Tj1 S_400_sic_var PARAMS: a={act} dVth={dVth} dR={dRdson} dgfs={dgfs} Inn={Inn} Unn={Unn}
+Rmax={Rmax} gmin={gmin} Rs={Rs} Rp={Rd} dC={dC} Rm={Rm}

...

.ENDS

With some ChatGPT help I concluded that the threshold voltage should be within 6.4V-8.8V, nominally 6.7V
This doesn't line up with diagram 10, showing the threshold voltage to go from ~5.2@-50C to ~3.5@175C, or the statement on the first page saying "Benchmark gate threshold voltage, VGS(th) = 4.5 V"


I also ran a simulation for diagram 11. Red line is at 25C and blue at 175C. This seems to line up with diagram 11

KlausST said:

you need to show a chart with V_GS AND V_DS.
The V_GS plateau is wher V_DS transitions.

It´s also a good idea to additionally show I_D, so we can see at which I_D is which V_GS.

Click to expand...

On the first plot the dark blue line is V_DS, the yellow line is the current through the inductor, and the light blue line is I_D of the lower MOSFET (current through the inductor + reverse recovery current of the upper MOSFET). Current through the inductor is 15.7A.

The way your simulation is set up won't produce plots resembling the datasheet.

Instead of driving the gate with a voltage source, instead drive it with a current source (i.e. a controlled charge per unit time). And the current should be very low (like <1mA) so that the switching is very slow.

Like below. Matches very well with the datasheet (gate current is 100uA, so t=400us corresponds to Qg=40nc):

HippopotamusXD said:

On the first plot the dark blue line is V_DS, the yellow line is the current through the inductor, and the light blue line is I_D of the lower MOSFET (current through the inductor + reverse recovery current of the upper MOSFET). Current through the inductor is 15.7A.

Click to expand...

Are you referring to post#6?

The picture is so blury I can´t see any value / text.
But I can see that the left side numbers are two digits only, so how can this show 200V of V_DS?

Klaus

See fig 4 and fig 5 of this...


Get those waveforms on your smps on the bench...if they dont look the same, ie
in relation to each other, then you have little hope of calculating switching losses using
any kind of "standard" method.
The stray inductances make nonsense of most "standard" methods for calc'ing sw losses

mtwieg said:

Instead of driving the gate with a voltage source, instead drive it with a current source (i.e. a controlled charge per unit time). And the current should be very low (like <1mA) so that the switching is very slow.

Click to expand...

I've tried that and just like you I got plots that line up with the ones in the datasheet. But I can't really understand why the small current is needed, as all of the sources I found when researching the plateau stated it's a function primarily of gate charge Q_g and in smaller extent V_DD and I_D, no sources mentioned it's a function of I_G. Do you maybe know of any resources I could read up on further?

I also noticed the plateau has got to do with the gate current when I tried varying the gate resistor from 1 to 10 Ohm and got the graph bellow, but once again this makes no sense to me.

KlausST said:

But I can see that the left side numbers are two digits only, so how can this show 200V of V_DS?

Click to expand...

Seems i only captured one Y axis when i took the screenshot, that axis shows the current, to the left of it there was another axis that was for V_DS that just goes from 200 to 0

HippopotamusXD said:

I've tried that and just like you I got plots that line up with the ones in the datasheet. But I can't really understand why the small current is needed, as all of the sources I found when researching the plateau stated it's a function primarily of gate charge Q_g and in smaller extent V_DD and I_D, no sources mentioned it's a function of I_G. Do you maybe know of any resources I could read up on further?

I also noticed the plateau has got to do with the gate current when I tried varying the gate resistor from 1 to 10 Ohm and got the graph bellow, but once again this makes no sense to me.

Click to expand...

Mainly two reasons:
1. The datasheet plot shows Vgs vs Qg. Your plots show Vgs vs time. The only way a transient simulation plotting Vgs vs time can resemble a plot of Vgs vs Qg is if Qg and time are proportional. You get that by driving the gate with a constant current Ig = dQg/dt.
It's also possible to extract the Vgs vs Qg plot when Ig is not constant, such as your simulation. But to do so you'll need to measure Qg vs time (by integrating the gate current), and then plotting Vgs vs Qg (may have to do this outside the simulator program).

2. At high speeds, your transistor model becomes much more complicated than a simple MOSFET. Parasitic resistance, inductance, and capacitance will start to distort the waveforms. To demonstrate this, here's the results of my simulation for three higher gate current values: 0.5A, 1.0A, and 2.0A:


The top subplot shows the external gate voltage, and it's highly distorted due to parasitic resistance and inductance in the subcircuit.
The middle subplot shows the Vgs of the actual MOSFET model inside the subcircuit. It still looks quite similar to the datasheet plot. But you can see that as things get faster it still gets increasingly distorted, so there are additional factors coming into play (mainly the drain capacitance slowing the fall of Vds, I think).

mtwieg said:

The top subplot shows the external gate voltage, and it's highly distorted due to parasitic resistance and inductance in the subcircuit.
The middle subplot shows the Vgs of the actual MOSFET model inside the subcircuit. It still looks quite similar to the datasheet plot. But you can see that as things get faster it still gets increasingly distorted, so there are additional factors coming into play (mainly the drain capacitance slowing the fall of Vds, I think).

Click to expand...

I think this is what I needed to hear, thank you very much