MOSFET blows in Electronic load design

[abicash]

Hi

I am trying to build a constant current Electronic Pulsed load for 0-5A dc.
Pulse width(single) is settable from 5mS to 1S. The current magnitude is set via a DAC of up to 5V corresponding to 5A.
The Load is a resistive load. MOSFET is mounted on a big solid heatsink.

Please find the schematic attached for reference.

I have tested the current pulse up to 5A for a compliance voltage of 30V. It works fine (perfect square wave voltage across the load) for various pulse widths. (Pulse width is one time for one switch press)
Now I had to increase the compliance voltage to 95 V for a load of up to 19 ohms.

Now when I send a pulse of 100mS for a current of 1A , the MOSFET shorted across all Gate, Drain, & Source.
I observed a square wave starting at 0 , then completing its 100mS for a straight line and at turn off , the voltage across the load shot north on the DSO.

What did I do wrong?

What do I need to correct for this to work?

Please help!

 

[D.A.(Tony)Stewart]

To understand the failure mode, consider parasitic wire inductance must be cancelled by twisted pairs and impedance control.

V=LdI/dt if >Vds max, this may cause a short circuit during turn-off.
To prevent this, use an ultra-fast diode clamp from drain to Vdd with a short path loop.

 

[dick_freebird]

A power MOSFET SOA has a "clipped corner" for power, that
allows less than rated drain voltage and rated drain current.
This is further subject to your cooling thermal impedance
stack from transistor guts to air @ flow.

I have had better luck making resistor loads like a "power
DAC" using wirewound dissipators and logic level FETs,
in my low voltage POL DC-DC efforts. There is no control
loop to freak out and no wish-it-was-linear operation of
power MOSFETs that were never meant for such things.

 

[barry]

A power MOSFET SOA has a "clipped corner" for power, that
allows less than rated drain voltage and rated drain current.
This is further subject to your cooling thermal impedance
stack from transistor guts to air @ flow.

I have had better luck making resistor loads like a "power
DAC" using wirewound dissipators and logic level FETs,
in my low voltage POL DC-DC efforts. There is no control
loop to freak out and no wish-it-was-linear operation of
power MOSFETs that were never meant for such things.

A one-time 100mS, 1A pulse is not going to cause enough power dissipation/heating to be of concern.

The problem here is, I suspect. some transient that occurred at turn-off. I question the use of that relatively large 1K gate resistor, but I can't see how that would cause the problem. I suspect it's a parasitic/layout problem.

 

[abicash]

A power MOSFET SOA has a "clipped corner" for power, that
allows less than rated drain voltage and rated drain current.
This is further subject to your cooling thermal impedance
stack from transistor guts to air @ flow.

wish-it-was-linear operation of
power MOSFETs that were never meant for such things.

I agree. I too have my doubt of the SOA for the MOSFET I used since the datasheet doesn't say anything about SOA below 100us!

--- Updated Apr 6, 2023 ---

A one-time 100mS, 1A pulse is not going to cause enough power dissipation/heating to be of concern.

The problem here is, I suspect. some transient that occurred at turn-off. I question the use of that relatively large 1K gate resistor, but I can't see how that would cause the problem. I suspect it's a parasitic/layout problem.

The 1k gate resistor is for loop compensation.

 

[D.A.(Tony)Stewart]

This is not modelled exactly to your layout, but it was not hard to simulate > 200V on Vds using the trailing edge. I reduced the ON time for trace convenience to see both edges. https://tinyurl.com/2986e2cv My original statement, holds true.

You can switch off the parasitic L with your cursor on the simulation, change Vdd, Vin and even add a clamp diode if you try.

Also reducing C29 increases dVgs/dt which accelerates LdI/dt greatly and thus Vds overvoltage while trading off bandwidth. If the load is non-linear you might need more BW.

 

[abicash]

This is not modelled exactly to your layout, but it was not hard to simulate > 200V on Vds using the trailing edge. I reduced the ON time for trace convenience to see both edges. https://tinyurl.com/2986e2cv My original statement, holds true.

You can switch off the parasitic L with your cursor on the simulation, change Vdd, Vin and even add a clamp diode if you try.

Also reducing C29 increases dVgs/dt which accelerates LdI/dt greatly and thus Vds overvoltage while trading off bandwidth. If the load is non-linear you might need more BW.

Thank you for the effort. Much appreciated.

So do you think that an ultrafast diode from the Drain to the Supply node may be able to protect the MOSFET short circuit from a probable parasitic inductance?
a UF4002 comes to mind.

 

[D.A.(Tony)Stewart]

Thank you for the effort. Much appreciated.

So do you think that an ultrafast diode from the Drain to the Supply node may be able to protect the MOSFET short circuit from a probable parasitic inductance?
a UF4002 comes to mind.

Any Si diode from Drain to Vdd can protect the overvoltage on NFET. A low pF or fast recovery diode just reduces high-frequency switching losses.
I simulated faster switching and used "any" default diode to show this simulates fine even with slew rate Cap removed. When the simulation indicates "convergence error" it means the sampling rate is too slow for the slew rate of the signal so sampling errors from over-voltage may occur. So I reduce the sim. sample time but this is limited to 2k samples or so for each plot.

When SMPS use this method of PWM to regulate the CV or CC, then ultra-fast diode clamps may be used. At some point at higher current loads, it ismore cost effective to replace the clamp diode with an active clamp switch, so a dual FET or half -bridge solution is preferred.

In some FETs the internal structure is like an array of parallel FETs but may have slightly different thresholds and RdsOn. A PTC tempco. is needed with fast transitions rather than slow analog gate controls in these types of FETs to avoid the thermal runaway of the internal junction well below rated current. Thus analog FET CC solutions must be used with caution or avoided.

eGaN® FET Safe Operating Area

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[KlausST]

Hi,

from the given informations .. there is no clear mistake.

So what´s wrong?
There are basicall only 3 problems killing a MOSFET: Voltage, current, power dissipation.

Voltage:
* the 12V supply needs to be properly bypassed with a fast capacitor to avoid ringin/ oscillation.
* the same is true for the 95V
* Maybe stray inductance (wiring, wire wound resisitors) causes a voltage peak
* maybe ESD. An ESD problem during handling, soldering could easily cause a long term fail.
--> an overvoltage protection on G-S and another one at D-S could be useful.

Current:
* did you first connect the load, then set the voltage? In other words: was the OPAMP output saturated at the positive supply when connecting the load? (mabe latched up, thus high and long overcurrent pulse)
* you say it´s up to 5A. In this case R29 will dissipate 25W. What exact resistor is this? --> link to datasheet.

Power dissipation:
* unlikely as long as the voltages and currents are correct.

Klaus

 

[dick_freebird]

I think that an E-load with 1K gate resistance has the potential to
act like a tank and you should eliminate the possibility of the one
pulse "starting something it can't stop".

For some applications (like "load slamming") a truly general purpose
linear E-load may be overkill that kills your schedule, to get right.
Might give some consideration to alternatives if this is more about
getting on with measurements, than the journey.

You need to be careful about believing in FET Pdiss numbers and
be sure you apply info to conditions. Power MOSFETs meant for
switching converters depend on two states ("on" and "off") with
minimal time spent between. For that case there are two power
dissipation scenarios. "Off", no current, swell. "On", high current,
low voltage and the bulk of the device electrical volume takes
the heat fairly uniformly (the drift region resistance). That's orderly
enough. If you fit the frame.

But there's another possibility. One consistent with weak gate
drive and one that I've blown up a bunch of integrated LDMOS
devices, trying to test. That is, a weakly energized gate and high
drain voltage (or medium, even). This scenario puts all the Pdiss
in the MOSFET "neck" region. This is a minuscule fraction of
device volume - maybe 1% of depth and a similar % of frontside
area - and can take a correspondingly lower heat flux (while
being right up against the fragile gate structure and aluminum
interconnect). In short pulse time you cannot invoke the full
device thermal path or heat-mass; you are looking at adiabatic
heating of a small volume. The device ratings avoid this as it's
a messy analysis and you can't guarantee every kooky misapplication
of what was meant to be a hard switching device.

 

[crutschow]

So do you think that an ultrafast diode from the Drain to the Supply node may be able to protect the MOSFET short circuit from a probable parasitic inductance?

Yes, that should help.
Connect the diode directly from the MOSFET drain terminal (anode) to the supply connection (cathode) near the resistor load.
Also connect a 100nF ceramic cap, plus a 10µF electrolytic directly from the cathode of the diode to the MOSFET source terminal.

 

[abicash]

Yes, that should help.
Connect the diode directly from the MOSFET drain terminal (anode) to the supply connection (cathode) near the resistor load.
Also connect a 100nF ceramic cap, plus a 10µF electrolytic directly from the cathode of the diode to the MOSFET source terminal.

I have the 95v generated from a Torroid transformer --> rectifier --> 5000uF/200V capacitor anyway.

 

[KlausST]

Hi,

Also connect a 100nF ceramic cap,

I just want to emphasize this.
current flows in a loop. If one part in this loop is "slow", maybe because of stray inductance, this will slow down the whole circuit. Then it does not matter anymore how fast the diode is, it will not be able to protect the MOSFET.

Thus: capacitor, short traces, fast diode .. all need to be fast.

Because of this, it´s often easier to use a fast MOV, transil, zener ... overvoltage protection directly across the D-S legs.

The benefit of the diode (Tony) is, that the current is fed back to the supply, thus improves overall performance, reduces heating.
The MOV ... solution just dissipates all the energy into heat.

Klaus

 

[abicash]

Hello

I realised one unknown action of this circuit.
As I explained previously , I have a voltage across a 5000uF capacitor as the compliance voltage.
I was being very careful , so I removed the connecting wire from the rectifier output to the +Cap and charged the capacitor to 55Vdc via a variable resistor and removed the input. The expectation is that the voltage across the capacitor remains constant , but what I observed is that it has a discharge curve of approximately 8mA .
I checked the voltage across the sense resistor , and there is some voltage drop across the sense resistor.
SO i removed the gate resistor from the MOSFET gate to the opamp, and connected a 10k across the gate and source of the MOSFET.
I find that this discharge stops now.
It seems the MOSFET is being triggered somehow. But unable to isolate the problem.

 

[KlausST]

Hi,

But unable to isolate the problem.

why not simply measure V_GS? I expect you to have a DVM.

One possible explanation is the OPAMP´s offset voltage. ...so that the OPAMP`s output never becomes zero.

Indeed I always avoid to go to theoretical limits. I never expect a circuit to work (inputs, outputs) at the supply rails.
In your case just use a voltage divider at the non-inverting input of the OPAMP to generate 25mV or so..

**

Also the "5V" DAC output has the same "close to rail" problem.

Klaus