MOSCAP @ nano meter process

[simonkuo]

Dear all
In the nano meter process, the MOS gate leakage is too large that I can't use it as a capacitor.
Does anyone have good idea to solve the issue ?
I have to use the MOS as a capacitor or use the capacitor magnified technique.
Does anyone ever survey the "capacitor magnified technique" ?

 

[huanchou]

Which circuit that you want to design?
PLL, regulator or ?
Try to use the thick oxide device.

 

[simonkuo]

I want to design a PLL by advance CMOS process, but dut to the leakage issue, it is hard to design by thin oxide device.
I have the area limitation, I can't use the thick oxide, MIM or Fringe CAP to design.
Does anyone have the good idea?

 

[ericzhang]

You can use the varactor cap(nmos in nwell) as PLL loop filter cap.

BR

eric
1/4

 

[simonkuo]

Thanks Eric!
The nmos in nwell still has the gate leakage issue.
Thin Oxide devices have the same issue and spice model doesn't have the model to simulate.

 

[xuel]

use thick oxide varactor or device