pankajpc
Junior Member level 1
Hi All,
I was wondering as to how to design CMOS switches for FFE for SERDES in 112GBPS. It is a quarter rate architecture. I am using PRBS data pattern but the switch is showing more output at sampling node (Node after sampling switch. where the sampling capacitor is put) then at the output of Source follower resistor (75 ohm) / CTLE/VGA which is after the PRBS input.
Is it possible that it may not be possible to do the same as we may have reached a fundamental physics limit.
Can you please share your opinion.
regards
-pankaj
I was wondering as to how to design CMOS switches for FFE for SERDES in 112GBPS. It is a quarter rate architecture. I am using PRBS data pattern but the switch is showing more output at sampling node (Node after sampling switch. where the sampling capacitor is put) then at the output of Source follower resistor (75 ohm) / CTLE/VGA which is after the PRBS input.
Is it possible that it may not be possible to do the same as we may have reached a fundamental physics limit.
Can you please share your opinion.
regards
-pankaj