MOS Mirrors - Accuracy...

Hi all,

simple, straight question: what is in your experience (i.e. possibly measured things) the maximum mirror ratio realizable without "tricks" like trimming (or what else?).
I mean, I can make a transistor "big at will" and I want to implement a current ratio of 1:n or n:1, what is the max value of n in your opinion/experience, and why?

Thank you in advance for your comments,

Michele

It depends on the technology and accuracy you want to achieve. At any rate, I implemented a (no-tricks but good layout) 1:300 mirrors with a 5-7% accuracy in 45nm. Layout is - of course - key, in this case.

Hi Joannes,

thank you for your reply. So that means - for the sake of putting numbers - that you have a ref current of 1uA and your output current is in the range of 300*(1±7.5)uA? (I'm taking your 5% as a plus/minus...Or is it ±5% what you intended?).

Now another question (which is actually the angle I'm looking from): if you had to implement a 300:1 mirror

1) it wouldn't make any sense, given that your error (5%) is larger than the 0.3% you'd like to achieve, or

2) we can assume that swapping input and output (and keeping the accurate layout) you will now get an error of 1/(300±1.075) for your output current (that is, again 1±0.25uA)?

Thanks,

Michele

I'm taking your 5% as a plus/minus...Or is it ±5% what you intended?

Click to expand...

%5 accuracy means ±2.5%.

1) it wouldn't make any sense, given that your error (5%) is larger than the 0.3% you'd like to achieve

Click to expand...

I just needed to multiply a bias current, the exact ratio was not important. I just reported to you what I achieved since you asked what is possible to achieve.

2) we can assume that swapping input and output (and keeping the accurate layout) you will now get an error of 1/(300±1.075) for your output current (that is, again 1±0.25uA)?

Click to expand...

If you re-mirror the current, your error would be (300/(300*(1±0.025)))*(1±0.025), or a final current between 0.9512uA and 1.0488. If it is just mirrored, you would have the same accuracy.

There are other concerns if the circuit is at all dynamic (as
most interesting ones, are). For example, that 1:300 mirror
with a 1uA feed, will probably have a lousy high frequency
PSRR and be kicked around by transient voltage excursions
because the gate node impedance is high and so is the
output Miller capacitance. A Wilson type would reduce
the gate node impedance but add another supply coupling,
and has limited authority against high-going blips. And so
on.

You would probably see worse accuracy effects from Vds
mismatch than natural mismatch.

You would be way ahead on area doing it in 2 stages
(say, 1:15 and 1:20), total 37 fingers, than 1:300 (301).

Point being, simple DC matching is certainly not the end-all.

Re: MOS Mirrors - Accuracy.....

JoannesPaulus said:

%5 accuracy means ±2.5%.I just needed to multiply a bias current, the exact ratio was not important. I just reported to you what I achieved since you asked what is possible to achieve.If you re-mirror the current, your error would be (300/(300*(1±0.025)))*(1±0.025), or a final current between 0.9512uA and 1.0488. If it is just mirrored, you would have the same accuracy.

Click to expand...

Thank you very much JoannesPaulus,

I would never have thought such accuracy to be possible. But this is just because I took for granted some "rules" without thinking about them critically.
I think the reasoning goes like this: the technology will give you some mismatch parameter like a variance/Area.
I know it is more involved than this¹, but for the sake of the basic idea: if you're targeting an accuracy of 5%, and you have a 300:1 ratio to implement, you would make your unity transistor as big (W*L) as to satisfy your matching criterion, right? So that

σ = M/√(W₁*L₁) = 5% [M is given by the tech]

And then organize 301 of these transistors in a nice layout...Maybe split the unity transistor into four pieces..
So, provided that my reasoning is correct (but, is it?), if you need an accuracy of x%, you just design your unity transistor to satisfy the area requirement given by your technology, and the "multiple" transistor will become as many times bigger as your required ratio.

I could then summarize it like this: "matching is no problem, as long as area is not a concern"

Correct?

M

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¹ because mismatch refers to fluctuations of process parameters, while we as designers are interested in, well, design parameters mismatch like Vt, β and ultimately current ratio or offset voltage, which have functional dependency on the process parameters, so that depending on the block the trade-offs involved in design are different: in mirrors you act on L, because it has the benefit of increasing the needed overdrive for a given current, thus minimizing Vt mismatch effect on mirror accuracy..While for diffpairs you act on W..

I could then summarize it like this: "matching is no problem, as long as area is not a concern"

Correct?

Click to expand...

Correct, cost is an issue too that good engineers must take into account!
Moreover, a comment on layout: depending on the technology, you have to take care of STI, WPE... organizing the layout to match the one transistor to the other 300 is non-trivial but can be done. Finally, dick_freebird's suggestion is highly recommended!

Hi Dick,

I had prepared a nice reply to you but it somehow got lost in the "re-login" process :x
Anyways, as I tend to do when there is a concept I can't grasp, I reduce it to a very simple - yet partial and not correct - type of problem.
The background of my question is that I come from a BiCMOS "school" where I used to aim for simple, "dynamically" limited ratios. Say 1:1-5 max.
Now I changed context completely, from Automotive RF to Consumer CMOS, and I keep finding designs with very "odd" ratios, like 11/3, which call for a type of accuracy I just deemed "impossible to obtain".
Well, as it turns out, I absorbed this "old school rule" of "healthy current ratios" without too much critical thinking, as the point is - exactly as you say - that matching is not the end-all. What escaped me is that - if you really want - you can achieve proper matching for "whatever" ratio. You do this at the expense of a larger area. Now, a larger area means bandwidth limitation and coupling parasitics (I'm sure these to be the points you address in your reply, although I can't picture what you refer to with the specific terms you use), so that if you add up all your constraints I am pretty sure you will end up by aiming for the good old "healthy ratios" I used to be acquainted with. But that's not for matching alone. The involved trade-off is broader than that.

Thank you for your comments!

M

Current mirrors - I agree with J.Paulus that on 45 nm you can do something like that. The reason is that process is a bit tighter controlled. With 45 gate length you can not have leff to vary too much. Let say 10% which gives you 4.5nm caused by underdiffusion etc. Now apply this to current miror which is L~0.5um - that L variation will be negligible!
Now on the other hand take 0.5um process - 10% variation will be huge. You can easily see this when you run montecarlo mismatch simulation on i.e 0.25um and 0.18um process. you get amazing comparison that 0.18 pretty much does not move while 0.25 is hard to match. Layout tricks or not.
For above 150nm technologies it is not safe to make more than 1:10 (max:20) mirroring. yes in case of sense fets it is 1:1000and more but then precision is not very good. For tighter geometries you can obviously do better.
Sure even i did way higher ratios but not for critical circuits.