MOS low or nul VT voltage threshold for analog

[okguy]

I have read many books about CMOS analog design, but ...
none of them mention a design with nul or low threshold voltage.
So, why so many foundries propose this 'analog' option ?
Which designs are using those VT ?

OkGuy

 

[khouly]

i think most of CMOS design books , provide u with the knowledge to design , then u know how to design, then u can use any technology avilable to u

like there are many technologies " .18 micro , .35 micro "
and so on

 

[gerryhsu]

I have read many books about CMOS analog design, but ...
none of them mention a design with nul or low threshold voltage.
So, why so many foundries propose this 'analog' option ?
Which designs are using those VT ?

OkGuy

The principle is the same. Low VT design happens in low-voltage communication chip,

 

[goodboy_pl]

by scaling devices more and more, supply voltage must be scaled too i.e. decreased.
in advanced processes like 0.18u the supply voltage is as low as 1.8 volts which makes the design of anlog/mixed mode ckts like Gm and opamps difficult, also the dynamic range of input ckts and switches drops dramatically, therefore this specific devices are added in mixed mode processes for simplifying the low voltage design.
NOTE: they are not suitable for digital design due to very high leakage current !

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