karthik225
Newbie level 1
![Newbie level 1](/styles/images/ranks/alevel1.gif)
Hello all,
I have implemented a MOS H bridge circuit to handle current upto 100uA as I need to bi-phasic current output.
When I change the direction of flow of current through the resistive load in the h bridge, I experience a very high glitch as shown in the picture below circled in red.
Could anyone suggest some solutions to reduce this glitch?
Thank you in advance.
PS: I am using high voltage transistors in 130nm CMOS technology.
![hbridge.jpg hbridge.jpg](https://www.edaboard.com/data/attachments/7/7731-a9d08784c8c35ed3b6c08c271d3cea24.jpg)
![hbridge_1.jpg hbridge_1.jpg](https://www.edaboard.com/data/attachments/7/7732-0f92790709edd78c3bd2ac4aa1b997cb.jpg)
I have implemented a MOS H bridge circuit to handle current upto 100uA as I need to bi-phasic current output.
When I change the direction of flow of current through the resistive load in the h bridge, I experience a very high glitch as shown in the picture below circled in red.
Could anyone suggest some solutions to reduce this glitch?
Thank you in advance.
PS: I am using high voltage transistors in 130nm CMOS technology.
![hbridge.jpg hbridge.jpg](https://www.edaboard.com/data/attachments/7/7731-a9d08784c8c35ed3b6c08c271d3cea24.jpg)
![hbridge_1.jpg hbridge_1.jpg](https://www.edaboard.com/data/attachments/7/7732-0f92790709edd78c3bd2ac4aa1b997cb.jpg)
moved to Analog IC Design & Layout [alexan_e]