MOS Enclosed Gate Layout

dick_freebird said:

In the industry this tends to be more "art in pocket" than
documented science. You will however find discussion of
it in various papers from IEEE NPSS society, especially the
NSREC conference publications and IEEE TNS. Which of course
the Irrelevant Ensemble would prefer you pay for while they
provide nothing back to the authors.

You will probably also find papers, and more accessible,
from ESA and CERN researchers.

The basic principle is, in junction-isolated or partially-depleted
SOI, that excess leakage and other gate-kink type misbehavior
comes from the bird's beak (LOCOS) or trench affected edges
of the active gate. So if you eliminate the edge you eliminate
the (or, that) problem.

Not to say you won't accrue others. For example, a common
annular gate geometry is drain inside, source outside. This is
best for speed and drive (minimize Cdb and Cdg, minimize Rs)
but you also then impose a 40% higher peak drain-gate field
at the inside corners (vector sum in the spacer oxide) which
may well violate the qualification paradigm of the foundry
and give you HCE you did not expect (but this, synergistic
HCE*radiation effects, is something that you ought to be
looking at yourself anyway).

Modeling is a little tricky as regards the true W, especially
as gate length increases (the channel becoming sort of
trapezoidal-donut, W at one end != W at the other end).
You can probably find formulae but they bear verifying
in silicon. You will change AS, AD, PS, PD and this can
be calculated from layout dimension pick-offs. This is
not about the compact model; it's just parameterization.

In FDSOI the annular gate may not help you, because
the back interface is not really under front-gate control
under a large range of bias conditions.

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