more thn one UseClause imports declaration of simple name "unsigned" none of the dec

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE work.my_data_types.all;
use ieee.std_logic_arith;
use ieee.numeric_std.all;
 
 
ENTITY Projem_With_adder IS
        
 GENERIC (n : INTEGER := 4);
 
 
PORT(   clk         : IN STD_LOGIC;
        --matris_in : IN integer_array(0 TO n+1);
        matris_out  : OUT int_arr_out;
        we          : in std_logic
        
        
);
end Projem_With_adder;
 
architecture behv of Projem_With_adder is 
 
SIGNAL matris_in :integer_array :=((0,0,0,0,0,0), (0,25,69,54,30,0), (0,215,14,3,98,0), (0,51,150,117,200,0), (0,100,13,82,9,0), (0,0,0,0,0,0)); 
SIGNAL s1,s2,s3,s4,s5,s6,s7,summary : std_logic_vector(7 downto 0);
VARIABLE counter : INTEGER;
 
TYPE state IS (st0,st1,st2,st3,st4);
SIGNAL pr_state,nx_state: state;
 
 
 
function adder (A,B : in integer) return unsigned is 
      
      variable tmp: unsigned(8 downto 0);
      variable SUM: unsigned(7 downto 0);
   begin
            
     --tmp :=  (conv_unsigned(A,8) + conv_unsigned(B,8) );
      
       -- G1 : FOR i IN 0 TO 7 LOOP
    --  if (A(i) XOR ( B(i) XOR CI )) =1 then
        --tmp(i) := '1';
 
        --else  tmp(i) := 0;
        
        --end if;
        --end LOOP;
      
      
        --SUM:=tmp (7 downto 0);
        --co:=tmp(8);
 
   return SUM; 
    
 end adder;
 
 
 
 BEGIN
 
 PROCESS(clk,we)
 
 BEGIN
 if(we='1') then
 pr_state <=st0;
 
 elsif(clk'event and clk = '1') then
 
 pr_state <= nx_state;
 
 end if;
 END PROCESS;
 
 PROCESS(pr_state,counter)
 
 BEGIN
  counter := 0;
   
  FOR i IN 1 TO n  LOOP
  FOR j IN 1 TO n  LOOP
 
 
 CASE pr_state IS
        WHEN st0 =>
        
        IF(counter = 0) THEN
 
        s1<=conv_integer(adder(matris_in(i-1,j-1),matris_in(i-1,j)));
        s2<=adder(matris_in(i-1,j+1),matris_in(i,j-1));
        s3<=adder(matris_in(i,j),matris_in(i,j+1));
        s4<=adder(matris_in(i+1,j-1),matris_in(i+1,j));
  
        counter:=counter + 1;
        nx_state <= st1;
        
        end if;
        
        WHEN st1 =>
        
        IF(counter = 1) then
        
        s5<=adder(s1,s2);
        s6<=adder(s3,s4);
        
        counter:=counter + 1;
        nx_state <= st2;
 
        end if;
        
        WHEN st2 =>
        
        IF(counter = 2) THEN
        
        s7<=adder(s5,s6);
        
        counter:=counter + 1;
        nx_state <= st3;
        
        end if;
        
        WHEN st3 =>
        
        IF(counter = 3) THEN 
        
        summary<=(s7,matris_in(i+1,j+1));
        matris_out(i,j)<=conv_integer(summary);
        
        end if;
        
        END CASE;
        
        
    
    
 
    
 
 end loop;
 end loop;
 end process;
 
 
 end behv;