cmos.analogvala
Newbie level 1
I have a model file for Mntecarlo Simulation for 90nm Process from a foundry for Cadence SPECTRE. I want to perform mismatch analysis considering actual layout of the circuit.
My chip has two modules which are far apart (say 6mm to 8mm apart) and the modules themselves are very small. I need to consider the fact that all Module A transistors are identical. All module B transistors are identical. However, transistors of module A and module B are not identical.
I want to incorporate correlation between neighboring transistors for Mismatch analysis. I could see an option to specify CC and transistor pairs in ADE/ Statistical Analysis. The question still remains what CC value should I give to the transistors located within the area of 60 lambda X 50 Lambda ? I understand this is also a proprietary information. However I just need a rough estimate.
Is CC=0.9 an for transistors in single module an educated approximation ?
-CA
My chip has two modules which are far apart (say 6mm to 8mm apart) and the modules themselves are very small. I need to consider the fact that all Module A transistors are identical. All module B transistors are identical. However, transistors of module A and module B are not identical.
I want to incorporate correlation between neighboring transistors for Mismatch analysis. I could see an option to specify CC and transistor pairs in ADE/ Statistical Analysis. The question still remains what CC value should I give to the transistors located within the area of 60 lambda X 50 Lambda ? I understand this is also a proprietary information. However I just need a rough estimate.
Is CC=0.9 an for transistors in single module an educated approximation ?
-CA